Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-10-23
2003-05-13
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06564353
ABSTRACT:
This application claims the benefit of Japanese Patent Application No. 2001-178295 filed on Jun. 13, 2001, which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1) Field of the Invention
The present invention relates to techniques suitable for the layout of a semiconductor integrated circuit such an integrated circuit (IC), a large-scale integration (LSI), etc., and more particularly a method and apparatus for automatically synthesizing and designing, in a design objective circuit, a clock distributing circuit (clock tree) which connects a clock-signal supplying element and clock-signal receiving elements together, and a computer readable storage medium storing a design program.
2) Description of the Related Art
Generally, in a semiconductor integrated circuit, a clock signal is supplied from at least one clock-signal supplying element (hereinafter referred to as a clock-supplying element) to a great number of clock-signal receiving elements such as flip-flops (hereinafter referred to as clock-receiving elements) through a clock distributing circuit. In such a semiconductor integrated circuit, there is an increasing demand for a higher-speed and larger-scale integrated circuit, and finning of circuit structure has advanced. Because of this, in order to make the best use of the performance of a semiconductor integrated circuit, it has been demanded to design a clock distributing circuit so that the clock skew and clock propagation delay time are optimized.
The clock propagation delay time used herein is the time needed for a clock signal to arrive from a single clock-supplying element at each clock-receiving element. Optimization of the clock propagation delay time is to reduce (or shorten) the delay time to the minimum. Also, the clock skew used herein is the difference between the timing at which a clock signal reaches one clock-receiving element (aforementioned clock propagation delay time) and the timing at which the same clock signal reaches another clock-receiving element (aforementioned clock propagation delay time). Optimization of the clock skew is to make the clock skew zero (in certain cases, to make it a desired value, not zero).
A conventional design method (method of optimizing clock skew and clock propagation delay time) for the semiconductor integrated circuit (clock distributing circuit) mentioned above is disclosed, for example, in Japanese Laid-Open Patent Publication Nos. HEI 2-62675, HEI 8-44776, and HEI 8-50604.
In the method of laying out logical circuit elements, disclosed in the aforementioned Japanese Laid-Open Patent Publication No. HEI 2-62675, logical circuit elements (clock-receiving elements) such as flip-flops are first laid out according to the connection relationship between them. Then, the number of clock amplifiers (drives) is determined and they are laid out. In this manner, the clock propagation delay time between the logical circuit elements is optimized.
In the method of designing a clock distributing circuit for a semiconductor integrated circuit, disclosed in the aforementioned Japanese Laid-Open Patent Publication No. HEI 8-44776, a clock tree is designed so that the occurrence of clock skew is suppressed. At the time of a logical design, each circuit element (clock-receiving element) is connected directly to a clock input buffer (clock-supplying element), and at the time of layout, clock buffers (drivers) corresponding to the number of circuit elements are laid out in tree form. Thereafter, wiring is performed between the clock buffers and the logical elements.
In the layout method of preventing clock skew, disclosed in the aforementioned Japanese Laid-Open Patent Publication No. HEI 8-50604, the occurrence of clock skew is prevented by making a fluctuation in the clock wiring length as small as possible. In this method, a plurality of clock-signal input terminals (clock-receiving elements) are divided into groups, and buffer cells (drivers) are inserted and laid out for each group. Thereafter, wiring is performed between the clock-signal output terminal, the buffer cells, and the clock-signal input terminals.
In the conventional methods mentioned above, basically, the number of buffers (drivers) and the number of stages are determined between a clock-supplying element and clock-receiving elements; then, net wiring is performed between the clock-supplying element, the clock-receiving elements, and the buffers; and the clock skew is adjusted (or optimized) by adjusting the state of the wiring (wiring length, wiring width, wiring shape, positions of branch points, etc.). However, to optimize the clock skew more reliably, it is preferable not to determine the number of buffers and the number of stages before the layout but rather to adjust the wired state and the positions of buffers at the time of the layout. Therefore, the development of such an optimization technique has been demanded.
Generally, to optimize clock propagation delay time, it is also desirable to generate a clock tree while taking the balance of the clock tree into consideration from the viewpoint of the density of clock-receiving elements laid out at predetermined positions. However, net wiring is often performed from a single clock-supplying element toward a great number of clock-receiving elements, and in such a method, it is possible to optimize clock skew, but it is extremely difficult to optimize clock propagation delay time at the same time.
SUMMARY OF THE INVENTION
The present invention has been made in view of the problems mentioned above. Accordingly, it is the object of the present invention to simultaneously and reliably optimize the clock propagation delay time and clock skew of the entire semiconductor integrate circuit, by determining a wiring path while adjusting both a wired state and layout of buffers from clock-receiving elements toward a clock-supplying element at the time of the layout, and then designing a clock distributing circuit.
To achieve this end, there is provided a method of designing a clock distributing circuit which distributes and supplies a clock signal from at least one clock-supplying element to a plurality of clock-receiving elements, comprising:
a temporary wiring step of temporarily wiring a signal line which directly connects the clock-supplying element with each of the clock-receiving elements disposed at predetermined positions, through the shortest path;
a judgement step of judging whether or not clock skew in the plurality of clock-receiving elements has been optimized by the signal line temporarily wired in the temporary wiring step;
a grouping step of dividing the plurality of clock-receiving elements into a plurality of groups when it is judged in the judgement step that the clock skew has not been optimized;
a buffer insertion step of (a) assigning a single buffer to each of the groups obtained by the grouping step, (b) selecting a plurality of buffer-insertion candidate positions where the buffer can be inserted and disposed, (c) temporarily wiring, for each of the selected buffer-insertion candidate positions, both a signal line which connects the buffer, disposed at the buffer-insertion candidate position, with each of the clock-receiving elements belonging to the group through the shortest path, and a signal line which connects the buffer, disposed at the buffer-insertion candidate position, with the clock-supplying element through the shortest path, (d) selecting a buffer-insertion candidate position, which can optimize clock skew and clock propagation delay time in the clock-receiving elements belonging to the group, from among the plurality of buffer-insertion candidate positions, based on temporary wiring results obtained for all of the plurality of buffer-insertion candidate positions, and (e) inserting and disposing the buffer at the selected candidate position; and
a final wiring step of determining wiring paths of signal lines which connect the clock-supplying element, the plurality of clock-receiving elements, and the buffer, according to the temporary wiring results obtained in the tempora
Liu Andrea
Staas & Halsey , LLP
LandOfFree
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