Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-07-27
2003-07-08
Nelms, David (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06591404
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to integrated circuit design. More particularly, it relates to a method for adding de-race buffers to maintain signal integrity in a circuit design having state elements and combinatorial elements.
BACKGROUND
An electronic circuit design may comprise both state elements, such as latches, and combinatorial elements, such as logic gates. As used herein, state elements include those elements capable of storing date over multiple clock cycles. In a state element, a change on an input results in a change at the output, if any, upon the receipt of a clock signal. Combinatorial elements refer to all other circuit elements that process input signals as they are received, rather than waiting for a clock signal. A design, or a portion of a design, may include both state elements and combinatorial elements interconnected, such that an output of a state element is connected to an input of a combinatorial element, and vice versa. A single clock signal may control multiple state elements in a design.
A timing problem occurs when a signal does not propagate through the circuit within specifications of the clock. A signal may have a maximum allotted time to pass from a source, such as an upstream state element, to a receiver, such as another state element located “downstream.” As used herein, that maximum time is referred to as the “max-time.” For example, a design may specify that a signal reaches a certain point in the circuit, such as the next state element, during a single clock cycle or a number of clock cycles. If the signal does not reach the specified point in the circuit within the max-time, a timing problem results and the circuit design does not meet the design's frequency goals. A signal may also have a minimum time allotted to pass from a source to a state element. Even though state elements may use the same clock input, the clock may be received at one state element later than it is received at another state element, for example due to clock skew. If a signal reaches a state element before the clock cycle, it may “race” through the state element, producing an incorrect output. The minimum time, referred to as the “min-time,” ensures that the signal does not reach the state elements before the appropriate clock cycle.
One way to ensure that the design meets the min-time specifications is to delay the signal by adding de-racing buffers, also referred to as “de-racers.” As used herein, de-racer refers to any element that delays a signal. Existing methods and systems require designers to place de-racers manually or as part of a complicated synthesis flow. This is a difficult task because a path from a source to a state element may have multiple signals entering and exiting. In some instances, it may be desirable to have a minimum number of de-racers in the circuit, so the de-racers may be positioned directly in front of recipient state elements. However, this implementation affects all paths to that state element when only some of the paths may have min-time problems. Moreover, addition of a de-racer may cause some paths to break their max-time specifications. A designer must ensure that the de-racer not only solves the min-time violation, but also keeps the design within max-time and other specifications. Addition of a de-racer may potentially cause max-time problems for other signals. In a complex circuit, this process generally requires the designer to analyze multiple signals along a path between state elements through a process of trial and error. What is needed is a more efficient method and system for resolving min-time violations.
SUMMARY OF INVENTION
A method is disclosed for resolving timing violations in a circuit design by adding de-racing buffers that slow selected signals to ensure that the signals do not arrive at a recipient state element too soon. A circuit design stored in memory has data including connectivity and timing information. This information is extracted to identify state elements with paths having min-time violations. The method attempts to resolve the min-time violations by inserting a de-racer at an instance at the end of the path, nearest the recipient state element. If the de-racer cannot be added to the instance, the method backtraces upstream along the path to the inputs of the next circuit element. The method attempts to de-race the inputs of that element by determining whether a de-racer would create a critical path to either the recipient state element or to another state element, for example if the output of the current gate drives another state element along another path. If any of the inputs cannot be de-raced, then the method backtraces again to the next upstream circuit element and repeats the process until a de-racer can be inserted, or until the method backtraces to the state element at the beginning of the path. The method may be used to create a new netlist containing connectivity of the circuit, including the de-race buffers. The new netlist may be input to a schematic generator to create a new schematic with the min-time violations fixed.
Some embodiments of the method use various refinements to resolve min-time violations. One embodiment first attempts to insert a partial de-racer having a certain delay time, but then attempts to insert a full de-racer having a greater delay time if a partial de-racer will not resolve the min-time violation. One embodiment replaces state elements, such as latches, with de-raced state elements or partially de-raced state elements in which the delay element is built into the state element. The method may be stored, for example, as computer-executable instructions on a computer-readable medium, and may be performed by a computer system having a memory that stores the circuit design.
A computer system is also disclosed for analyzing a circuit design and attempting to resolve min-time timing violations by adding de-racing buffers. A circuit design stored in memory has data including connectivity and timing information. The system extracts this information to identify paths having min-time violations. Beginning at the input of the state element, the system attempts to resolve the min-time violations by inserting a de-racer. If the de-racer cannot be added to the instance, the system backtraces upstream along the path to the inputs of the next circuit element and attempts to de-race the inputs of that element The system uses a de-race function, to determine whether buffer would create a critical path to the recipient state element or to another state element. If all inputs having min-time violations cannot be de-raced, then the system continues to backtrace upstream along the path until a de-racer may be inserted or until the sending state element is reached. A forward update function updates the timing information in the circuit design stored in memory to include the de-racers added.
REFERENCES:
patent: 6044209 (2000-03-01), Alpert et al.
patent: 6080201 (2000-06-01), Hojat et al.
patent: 6212666 (2001-04-01), Gohl et al.
patent: 6347393 (2002-02-01), Alpert et al.
Le Thao
Nelms David
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