Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2001-07-20
2003-05-06
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S239000, C438S240000, C438S253000
Reexamination Certificate
active
06559025
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and method for manufacturing semiconductor devices, and more particularly, to a capacitor of a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
Capacitors of highly integrated memory semiconductor devices, such as a large capacity dynamic random access memory (DRAM) and a ferroelectric random access memory (FRAM), include dielectric layers made of materials such as PZT (PbZrTiO
3
) and BST (BaSrTiO
3
), which have a high dielectric constant. Electrodes in these capacitors are often made of a metal from the platinum group or an oxide of a platinum group metal. However, forming and dry etching of platinum group metals and the their oxides often present difficulties. Further, the metals and oxides are prone to react with semiconductor substrates or polysilicon plugs. Accordingly, a diffusion barrier layer is required between the conductive layer and semiconductor materials such as polysilicon.
FIG. 1
illustrates a semiconductor device including a conventional capacitor having a dielectric layer with high dielectric constant. Referring to
FIG. 1
, a first insulating layer
3
having a contact hole
2
is on a semiconductor substrate
1
, and a polysilicon contact plug
5
and a tantalum (Ta) diffusion barrier layer
7
are in contact hole
2
. An etch stop layer
9
and a third insulating layer
11
are sequentially formed on first dielectric layer
3
overlying semiconductor substrate
1
and patterned to expose diffusion barrier layer
7
and adjacent portions of first insulating layer
3
.
A storage node
13
is on the inner wall of the opening in third insulating layer
11
and on the exposed portions of diffusion barrier layer
7
and first insulating layer
3
. A BST dielectric layer
15
is on storage node
13
, and a ruthenium (Ru) plate node
17
is on dielectric layer
15
.
Diffusion barrier layer
7
suppresses reactions between storage node
13
and contact plug
5
. However, in the conventional capacitor of
FIG. 1
, the storage node
13
is thin, and deposition of dielectric layer
11
or subsequent annealing can oxidize diffusion barrier layer
7
into a Ta
2
O
5
insulating layer. Thus, the contact resistance between storage node
13
and substrate
1
increases. Further, the chemical mechanical deposition that forms ruthenium storage node
13
leaves an irregular surface morphology, resulting in regions of storage node
13
with concentrated electric fields when the capacitor is in use. These high electric field regions can increase leakage current of the capacitor.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for manufacturing a capacitor of a semiconductor device. The method includes: forming a first insulating layer having a contact hole on a semiconductor substrate; forming a diffusion barrier layer in the contact hole, wherein the diffusion barrier layer electrically connects to the semiconductor substrate; forming a second insulating layer and a third insulating layer sequentially on the first insulating layer, wherein a hole is formed in the second insulating layer and third insulating layer to expose the diffusion barrier layer; forming a conductive layer on the semiconductor substrate such that the conductive layer covers the inner wall of the hole in the second insulating layer and third insulating layer; forming an insulating fill layer that fills the remainder of the hole containing the conductive layer; removing upper portions of the fill layer until the third insulating layer is exposed but a portion of the fill layer remains in the hole; removing the third insulating layer to expose the second insulating layer; forming a dielectric layer on the semiconductor substrate, wherein the dielectric layer covers remaining portions of the fill insulating layer, the second insulating layer, and the conductive layer; and forming a plate node on the dielectric layer.
Forming the conductive layer on the inner surface of a hole in the insulating layers provides the conductive layer with a smooth surface that is later covered by the dielectric layer. Additionally, the presence's of the second insulating layer between storage electrodes and filling the cavity in the conductive layer prevents diffusion of oxygen and oxidation of the diffusion barrier layer.
REFERENCES:
patent: 5293510 (1994-03-01), Takenaka
patent: 5392189 (1995-02-01), Fazan et al.
patent: 5488011 (1996-01-01), Figura et al.
patent: 5504041 (1996-04-01), Summerfelt
patent: 5619393 (1997-04-01), Summerfelt et al.
patent: 5773314 (1998-06-01), Jiang et al.
patent: 5801079 (1998-09-01), Takaishi
patent: 6060735 (2000-05-01), Izuha et al.
patent: 6136660 (2000-10-01), Shen et al.
patent: 6162744 (2000-12-01), Al-Shareef et al.
Y. Kohyama, et al.; “A Fully Printable, Self-aligned and Planarized Stacked Capacitor DRAM Cell Technology for 1Gbit DRAM and Beyond”; 1977 Symposium on VLSI Technology Digest of Technical Papers; 2 pages (PP. 17 and 18).
Harness & Dickey & Pierce P.L.C.
Malsawma Lex H.
Samsung Electronics Co,. Ltd.
Smith Matthew
LandOfFree
Method for manufacturing a capacitor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing a capacitor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a capacitor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3086752