Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-02-28
2003-03-25
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S623000, C438S624000, C438S634000, C438S637000, C438S672000
Reexamination Certificate
active
06537908
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to interconnects for various semiconductor devices including high-speed microprocessors, application specific integrated circuits (ASICs) and other high-speed integrated circuits (ICs). More specifically, the present invention relates to a method to carry out a dual damascene process for copper, Cu, and low dielectric constant, i.e., low-k, interconnects based on a distributed hard mask. The inventive method provides a simple process which has fewer processing steps than conventional prior art patterning methods; therefore, a reduction in cost compared to prior art patterning methods can be obtained.
BACKGROUND OF THE INVENTION
Interconnect structures containing low-k dielectrics (on the order of about 3.5 or less), as the interlevel dielectric, and Cu, as the wiring or via levels, of the dual damascene-type are known in the prior art; See, for example, R. D. Goldblatt, et al., “A High Performance 0.13 &mgr;m Copper BEOL Technology with Low-K Dielectric”, Proceedings of the International Technology Conference, IEEE Electron Devices Society, Jun. 5-7, 2000 pgs 261-263. Commonly, prior art methods to fabricate Cu interconnect structures of the dual damascene-type in a polymeric low-k dielectric use hard mask layers that are deposited in a vacuum-based plasma-enhanced chemical vapor deposition (CVD) tool or by other deposition processes such as high density plasma, etc. The polymeric low-k dielectric, on the other hand, is formed by means of a spinn on coating tool.
A typical prior art process for forming a dual damascene-type Cu interconnect structure is shown in FIGS
1
A-
1
E. Specifically,
FIG. 1A
shows an initial structure which includes interlevel dielectric
10
having hard mask layer
12
comprising polish stop layer
14
and patterning layer
16
formed thereon. As is illustrated, polish stop layer
14
is formed on the surface of the interlevel dielectric and patterning layer
16
is formed on the polish stop layer. In these drawings, interlevel dielectric is a low-k dielectric material having a dielectric constant of from about 3.5 or less which is formed on a substrate (not shown) by means of spin coating. Polish stop layer
14
and patterning layer
16
are formed on the interlevel dielectric by using plasma-enhanced CVD. It is noted that the polish stop layer and patterning layer of the hard mask are chosen to have different etching rates which allows for the formation of vias and/or lines in the interlevel dielectric.
Following the formation of the hard mask on the surface of the interlevel dielectric, a photoresist (not shown) is formed on an exposed surface of the patterning layer and a pattern is formed in the resist by conventional lithography including resist exposure and development. The pattern is then transferred to the patterning layer, stopping on the polish stop layer utilizing a conventional etching process such as reactive-ion etching (RIE). The photoresist used in opening the patterning layer is then removed by conventional means providing the structure shown in FIG.
1
B.
The polish stop layer is then opened by applying a second photoresist to the hard mask (not shown in the drawings) and subjecting the same to lithography and etching. The second resist is stripped providing the structure shown in FIG.
1
C. Note that this step provides opening
18
in the polish stop layer which exposes a surface of the interlevel dielectric.
The interlevel dielectric is then subjected to an etching process so as to remove exposed portions of the interlevel dielectric such as shown in FIG.
1
D. Cu or another conductive metal
20
is then deposited in the etched areas of the interlevel dielectric and thereafter the structure is subjected to a conventional planarization process to form the structure shown in FIG.
1
E. Note that the final structure does not include the patterning layer, but does include the polish stop layer.
Not only are PECVD tools costly to purchase and manufacture, but also the use of both a PECVD tool and a spin-on coating tool in fabricating the Cu interconnect structure leads to increased raw processing time (RPT) due to the required transfer of wafers between tools. Also, current polish stop layers have a relative dielectric constant, k, of about 4 to 7, which is significantly greater than that of the low-k dielectric used in forming the interlevel of the interconnect structure. Since the effective dielectric constant of the device is dependent on the summation of all the dielectrics present in the structure, the presence of a polish stop layer having a high-dielectric constant would lead to an increased effective dielectric constant and loss of circuit performance.
In view of the drawbacks mentioned in the prior art methods of fabricating Cu interconnects of the dual-damascene-type, there is a continued need for developing a new and improved method of fabricating a Cu dual damascene-type structure which does not significantly increase the effective dielectric constant of the device. Moreover, a method is needed that is simple to use, yet reduces the number of processing steps and therefore cost of the overall process. Such a method would represent a significant improvement over prior art methods of fabricating a Cu interconnect structure of the dual-damascene-type.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating a Cu interconnect structure that includes a low-k dielectric that includes one tool for manufacturing both the low-k dielectric and the hard mask, i.e., polish stop and patterning layers.
Another object of the present invention is to provide a method of fabricating a Cu interconnect structure containing a low-k dielectric interlevel wherein the effective dielectric constant of the resultant device is not significantly increased.
A further object of the present invention is to provide a method of fabricating a Cu interconnect structure containing a low-k dielectric in which both the hard mask and the low-k dielectric are cured in a single step, rather than multiple curing steps as is required by prior art patterning methods.
An additional object of the present invention is to provide a method of fabricating a Cu interconnect structure containing a low-dielectric wherein PECVD is not employed to deposit the hard mask, i.e., patterning and polish stop layers.
These and other objects and advantages are achieved in the present invention by utilizing a method wherein a spin-on coating tool is employed in forming both the low-k dielectric material as well as the hard mask, i.e., polish stop and patterning layers, of a dual damascene-type interconnect structure. Since both layers of the hard mask are formed by spin-on coating, the use of conventional PECVD tools is eliminated; therefore reducing the cost of the overall manufacturing process.
Specifically, the patterning method of the present invention comprises the steps of:
(a) spin-on coating a dielectric material having a dielectric constant of about 3.5 or less on the surface of a substrate;
b) forming a hard mask comprising at least a polish stop layer and a patterning layer on a surface of said dielectric material, wherein said polish stop layer and said patterning layer have different etching rates and are both formed by spin-on coating and said polish stop layer has a dielectric constant that is compatible with said dielectric material and has an etch selectivity to said dielectric material, and said patterning layer has an etch selectivity to said polish stop layer;
(c) curing said hard mask and said dielectric material;
(d) forming an opening in said hard mask so as to expose a portion of said dielectric material;
(e) etching said exposed portion of said dielectric material so as to form a trench in said dielectric material;
(f) filling said trench with at least a conductive metal; and
(g) planarizing said conductive metal stopping on the uppermost surface of said polish stop layer.
REFERENCES:
patent: 4959583 (1990-09-01), Brewer et al.
patent: 5482894 (1996-01-01), Haveman
Fornof Ann Rhea-Helene
Gates Stephen McConnell
Hedrick Jeffrey Curtis
Nitta Satyanarayana V.
Purushothaman Sampath
Guerrero Maria
International Business Machines - Corporation
Morris Daniel P.
Scully Scott Murphy & Presser
Zarabian Amir
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