Method of manufacturing a semiconductor device

Details Method of manufacturing a semiconductor device Method of manufacturing a semiconductor device

2001-08-30

2003-05-13

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S781000, C438S789000, C438S790000

Reexamination Certificate

active

06562732

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a method of manufacturing a semiconductor device, comprising the provision of a dual damascene structure which comprises a metal layer on which a first dielectric layer provided with a via is present, a second dielectric layer disposed on the first dielectric layer and provided with an interconnect groove, in which via and which interconnect groove a metal is present which forms a metal line having an upper side.
DESCRIPTION OF THE RELATED ART
Such a method is known from WO-A-0 019 523. In the known method, a first metal wiring pattern is obtained on a substrate, on which pattern a first layer of insulating material with a low dielectric constant, also referred to as “low-k” dielectric layer, is provided. A layer is provided thereon which acts as an etch stopper and in which a via pattern is provided. Then a second low-k dielectric layer is provided, on which a mask is formed. The mask is patterned, and a groove is etched into the second low-k dielectric layer by means of this mask down to the etch stopper layer. Etching then continues through the first low-k dielectric layer, so that a via is formed. The groove and the via are filled with metal such that this metal comes into electrical contact with the subjacent metal layer. The excess metal is removed, and a substantially planar upper side is formed.
Given the present development, in which the dimensions of integrated circuits become ever smaller, it is desirable to obtain a capacitance between the various conductors which is as low as possible. This may be achieved through the use of air gaps. According to the known techniques, however, it is not very well possible to form air gaps in dual damascene structures.
SUMMARY OF THE INVENTION
The invention has for its object inter alia to provide a method of the kind described in the opening paragraph whereby air gaps can be formed next to the metal line.
According to the invention, the method is for this purpose characterized in that the method further comprises the following steps:
removal of the second dielectric layer,
provision of a disposable layer on the first dielectric layer and the metal line,
planarizing the disposable layer down to the upper side of the metal line,
provision of a porous dielectric layer on the disposable layer, and
removal of the disposable layer through the porous dielectric layer so as to form air gaps.
The use of a disposable layer for the formation of air gaps is known per se from U.S. Pat. No. 5,461,003. The method described in this document, however, is not directly applicable to a dual damascene structure. The metal line lies recessed in dielectric material in a dual damascene structure. The invention is based on the recognition that a process is to be used for obtaining exposed metal lines between which air gaps can be formed. It is especially the first step in the characterizing portion of the method according to the invention which ensures this.
An embodiment of the method according to the invention is characterized in that an etch stopper layer is present between the first dielectric layer and the second dielectric layer. The use of an etch stopper layer is known per se from WO-A-0 019 523. In this document, however, the layer is used as a hard mask for forming the via in the first dielectric layer. In the method according to the invention, the layer is also used as an etch stopper during the removal of the second dielectric layer after the formation of the dual damascene structure. An advantage of the etch stopper layer in the application according to the invention is that the first dielectric layer is shielded during the removal of the second dielectric layer and is not influenced by the etching process.
A further embodiment of the method according to the invention is characterized in that a non-conductive barrier layer is provided over the metal line after the removal of the second dielectric layer. Since the metal line is fully enclosed by this barrier, electromigration problems are counteracted.
In another embodiment a conductive barrier layer is provided over the metal line and the planarized disposable layer, and that the conductive barrier layer is structured by polishing so as to over the metal line only. The structuring of the conductive barrier layer is in fact a self-aligned process, and is known from JP 2000-195864. Suitable conductive barrier materials are for instance, Ta, Tin, TaN, W, TiNW. An advantage of the embodiment is that the metal, preferably copper, is capsulated. Due to the structuring the conductive barrier layer does not inhibit the removal of the decomposition products of the disposable layer through the porous dielectric layer. Another advantage, compared to the use of a non-conductive barrier layer is that the conductive barrier layer is not part of the dielectric between metal lines. Hence, the parasitic capacitance is decreased.
A further embodiment of the method according to the invention is in effect, the porous dielectric layer is thus any layer that permeable for gaseous molecules characterized in that a spin-on material is used for the porous dielectric layer. The provision of a porous dielectric layer by means of a spin coating process which is known per se has the advantage that such a process takes place at a low temperature. This low temperature renders it possible, for example with the use of a polymer as the disposable layer, to avoid problems such as premature degradation of the polymer.
A further embodiment of the method according to the invention is characterized in that a plasma CVD layer is used for the porous dielectric layer. An advantage of this that a plasma CVD (Chemical Vapor Deposition, known to those skilled in the art) layer provides an additional strength in the structure obtained by the method according to the invention.


REFERENCES:
patent: 5461003 (1995-10-01), Havemann et al.
patent: 6071809 (2000-06-01), Zhao
patent: 6265321 (2001-07-01), Chooi et al.
patent: 0911697 (1999-04-01), None
patent: 195864 (2000-07-01), None
patent: 0019523 (2000-04-01), None

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