Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-12-01
2003-04-01
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S403000, C257S407000, C257S345000, C257S372000
Reexamination Certificate
active
06541829
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
The subject application claims benefit of the earlier filing dates of Japanese Patent Application Nos. Hei 11-345426 and 2000-12107 filed on Dec. 3, 1999 and Jan. 20, 2000 under the Paris Convention, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices such as MISFETs (metal insulator semiconductor field-effect transistors) capable of suppressing threshold voltage (Vth) variations due to a short channel effect or manufacturing variations. In particular, the present invention relates to MISFETs' impurity concentration profiles including channel impurity concentration profiles and counter impurity concentration profiles.
2. Description of the Related Art
It has been warned that micronization of a MISFET increases the influence of channel impurity concentration variations on Vth variations, to deteriorate the characteristics of the MISFET.
A CMOS (complementary metal oxide semiconductor) circuit may have a pMOSFET with an n
+
polysilicon gate and a counter-doped channel surface. The counter-doped channel surface has an opposite conductivity type from a channel conductivity type, thereby forming a buried channel. The buried channel will suffer from a short channel effect if the counter-doped channel surface is deep. The short channel effect is a phenomenon that a threshold voltage (Vth) drops as a gate length is shortened. When micronized, the pMOSFET must have a short gate length. If the gate length is shortened to a lithography control limit, a gate length variation will account for a significant part of the gate length and the short channel effect will vary the electric characteristics of the pMOSFET, to deteriorate yield of CMOS circuits. A micronized CMOS circuit must employ a low source voltage. To decrease source voltage, it is necessary to decrease the threshold voltage (Vth) of a transistor. The threshold voltage, however, increases in proportion to a substrate impurity concentration, which must be high to suppress the short channel effect. Namely, increasing a substrate impurity concentration to suppress the short channel effect results in deteriorating transistor characteristics.
To solve this problem, a counter-doped layer of high impurity concentration may be formed at the surface of a substrate. This may increase a substrate impurity concentration to suppress the short channel effect. The counter-doped layer of high impurity concentration, however, must be very shallow to provide a low Vth value. It is difficult to form such a shallow, high-impurity-concentration, counter-doped layer because the counter-doped layer is inevitably thickened by thermal impurity diffusion during high-temperature processes such as a gate insulating film forming process and an impurity activation process.
As mentioned above, a buried channel is formed when a channel impurity layer is counter-doped. For example, an n-type impurity distribution having a gentle concentration profile is formed in a substrate, and p-type impurities are introduced into a shallow area of the substrate to cancel the n-type impurity distribution at the substrate surface, as disclosed by I. C. Kizilyalli et al. in “N
+
-Polysilicon Gate PMOSFETs with Indium Doped Buried-Channels,” IEEE Electron Device Letters, vol. 17, pp 46-49, 1996. This technique introduces p-type counter impurities to form a shallow p-type region in a substrate. Compared with a deep profile, the shallow profile forms a channel closer to the substrate surface, to prevent an increase in the effective thickness of a gate insulating film and suppress the short channel effect. To cancel a high n-type impurity concentration around a pn junction, the p-type impurities to be introduced must be of high concentration. MOSFETs with buried channels and n
+
polysilicon gates are known to involve large Vth variations.
To meet a low source voltage, nMOSFETs as well as pMOSFETs are required to have low Vth values. A low Vth value is achievable by counter doping even if a channel impurity concentration is high. MOSFETs conventionally employ polysilicon gates that involve high gate resistance to hinder micronization. The gate resistance is reducible by replacing the polysilicon gates with metal gates. The metal gates provide a high work function, and therefore, an nMOSFET having a metal gate and a buried channel will simultaneously realize a low Vth value and a high channel impurity concentrations to suppress the short channel effect, as disclosed by A. Chatterjee et al. in “CMOS Metal Replacement Gate Transistors Using Tantalum Pentoxide Gate Insulator,” IEDM 98, pp 777-780, 1998. However, there are no reports that described how to realize a low Vth value with a metal gate. It is even claimed that a surface channel is superior to a buried channel for a metal gate because the buried channel involves large Vth variations. Namely, a large problem with the metal gate is a channel impurity concentration profile.
SUMMARY OF THE INVENTION
As mentioned above, buried-channel MOSFETs involve large Vth variations, and the cause of such Vth variations has been unclear. The inventors clarify the cause as follows.
FIG. 1
is a model showing a typical impurity concentration profile in a semiconductor substrate under a gate oxide film of an nMOSFET having a buried channel. A horizontal axis represents depths from an interface between the gate oxide film and the surface of the substrate. A vertical axis represents impurity concentrations. A channel impurity concentration profile
1
represents a p
+
region containing channel impurities and is high and unchanged from the substrate surface to the inner part of the substrate. A counter impurity concentration profile
2
represents a counter-doped n
+
impurity layer whose conductivity type is opposite to the conductivity type of the channel impurity region. The counter profile
2
extends from the substrate surface to a depth of 10 nm. The counter profile
2
is higher than the channel profile
1
and is unchanged. Based on these profiles
1
and
2
, Vth variations will be simulated.
FIG. 2
is a graph showing simulation results on typical buried channel structures. The graph shows counter impurity concentrations and corresponding threshold voltage (Vth) values, as well as counter impurity concentration variations and corresponding Vth variations. The simulations are based on a source voltage of 1 V and a drain electrode receiving 1 V to measure each Vth value. The channel impurity concentration profile
1
of
FIG. 1
has a concentration of 2×10
18
cm
−3
. In
FIG. 2
, an abscissa represents counter impurity concentrations and an ordinate Vth values and Vth variations due to variations in the counter impurity concentration profile
2
of
FIG. 1. A
curve with “+” marks indicates Vth values. A curve with squares indicates Vth variations when the counter profile
2
of 10 nm deep is made shallower by 0.5 nm to 9.5 nm. A curve with “&Dgr;” marks indicates Vth variations when the impurity concentration of the counter profile
2
is reduced by 2%. These depth and concentration variations were selected to correspond to actual semiconductor device manufacturing variations. In
FIG. 2
, a low Vth value of 0.4 V is achievable with an increased counter impurity concentration of 5.3×10
18
cm
−3
. At this concentration, the 0.5-nm-deep variation curve indicates a Vth variation of 50 mV, and the 2%-concentration variation curve indicates a Vth variations of 10 mV.
The cause of such variations will be studied in connection with an nMISFET.
A threshold voltage Vth of the MISFET is determined by a net impurity concentration profile irrespective of a channel impurity concentration profile or a counter impurity concentration profile. The net profile is a profile of net impurity concentrations, and each net in purity concentration is the absolute value of a difference between a p-type impurity concentration and an n-type i
Akasaka Yasushi
Nishinohara Kazumi
Suguro Kyoichi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hu Shouxiang
Kabushiki Kaisha Toshiba
Loke Steven
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