Semiconductor memory device with variably set data...

Details Semiconductor memory device with variably set data... Semiconductor memory device with variably set data...

2002-03-01

2003-07-08

Le, Vu A (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S189050, C365S193000

Reexamination Certificate

active

06590796

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device which has variably set data input-output terminals and control signal terminals for the same, in which there is a common supply of control signals regardless of the byte configuration of the data input-output terminals, so that variation in the data input-output timing and variation in the data mask timing according to the byte configuration is prevented.
2. Description of the Related Art
In semiconductor memory devices, there has been a proliferation of devices of various types with different memory cell structures, such as DRAM, SRAM, flash memories, ferroelectric memories and the like. These memory devices have different memory cell structures; however, addresses, data and commands such as read-write commands and the like are supplied from the outside, read data is output at a specified timing, and write data is similarly input.
Memory devices must have a configuration which can handle various types of data input-output terminal configurations such as a 4-bit configuration, 8-bit configuration, 16-bit configuration or the like in accordance with the configuration of the system in which the memory device is mounted. On the other hand, the design and production of separate memory devices for a plurality of different types of input-output bit configurations results in an increase in cost. Accordingly, such a cost increase is prevented by suing a common memory circuit, a common chip and a common package, and arranging the system to a plurality of different types of memory devices so that used and unused pins or used and unused data input-output terminals can be altered in accordance with the input-output bit configuration.
FIGS. 1
,
2
and
3
are diagrams which illustrate the configurations of conventional memory devices.
FIG. 1
shows a memory device in which the data input-output terminals have a 2-byte or 16-bit configuration,
FIG. 2
shows a memory device in which the data input-output terminals have a 1-byte or 8-bit configuration, and
FIG. 3
shows a memory device in which the data input-output terminals have a ½-byte or 4-bit configuration. One of these memory devices is selected in accordance with the system in which the memory device is mounted.
In the figures, a chip
1
on which a memory circuit is formed is mounted in a package
2
. In order to handle the three types of memory devices described above, the chip
1
has 16 data input-output terminals DQ
0
to DQ
7
and DQ
8
to DQ
15
, and input-output buffers IO-BUF
0
to IO-BUF
15
that correspond to these data input-output terminals, and the package
2
has external pins P
0
to P
15
. Furthermore, the chip
1
has strobe signal terminals STB
0
and STB
1
that control the data input-output timing, and corresponding input-output buffers IO-BUFS
0
and IO-BUFS
1
for each of the 8-bit (1-byte) data input-output terminal groups DQ
0
to DQ
7
and DQ
8
to DQ
15
, and the package
2
also has corresponding external pins PS
0
and PS
1
. Furthermore, the chip
1
has mask signal terminals MSK
0
and MSK
1
used to prohibit data input-output for each of the 8-bit (1-byte) data input-output terminal groups DQ
0
to DQ
7
and DQ
8
to DQ
15
, and the package
2
also has corresponding external pins PS
0
and PS
1
. The terminals of the chip and the external terminals of the package are connected by bonding wires
3
.
In computer systems in which memory devices are mounted, data is generally processed in word units (1 byte or 8 bits). Accordingly, memory devices are also correspondingly constructed so that the timing control signals are utilized in respective data input-output terminal groups consisting of word units (1 byte or 8 bits).
In the case of the 16-bit configuration shown in
FIG. 1
, a strobe signal terminal STB
0
and a mask signal terminal MSK
0
are provided for the first data input-output terminal group DQ
0
to DQ
7
, and a strobe signal terminal STB
1
and mask signal terminal MSK
1
are provided for the second data input-output terminal group DQ
8
to DQ
15
. To describe the strobe signals STB
0
and STB
1
, switches SW
0
and SW
1
are installed in strobe signal supply lines
10
and
20
that supply strobe signals to the respective data input-output buffers inside the chip
1
; here, the switch SW
0
is controlled to a conductive state, while the switch SW
1
is controlled to a non-conductive state. As a result, the first strobe signal STB
0
is supplied to the first data input-output buffer group IO-BUF
0
to IO-BUF
7
, and the second strobe signal STB
1
is supplied to the second data input-output buffer group IO-BUF
8
to IO-BUF
15
. These switches are controlled by set signals L
4
, L
8
and L
16
generated by a latching circuit
4
which latches that data input-output terminal configuration.
Furthermore, the first mask signal MSK
0
controls the writing operation of the write amplifier WA
0
-WA
7
corresponding to the first data input-output signals DQ
0
to DQ
7
, and the second mask signal MSK
1
controls the writing operation of the write amplifier WA
8
-WA
15
corresponding to the second data input-output signals DQ
8
to DQ
15
.
Thus, strobe signals and mask signals are provided for each of the 8-bit data input-output terminal groups, so that the input-output buffers and write amplifiers of the respective subordinate data input-output terminal groups are controlled.
In the case of the 8-bit configuration shown in
FIG. 2
, as is indicated by the bonding wires
3
, only the four bits DQ
0
, DQ
2
, DQ
5
and DQ
7
are used from the first data input-output terminal groups DQ
0
to DQ
7
, and only the four bits DQ
8
, DQ
10
, DQ
13
and DQ
15
are used from the second data input-output terminal group DQ
8
to DQ
15
. The other data input-output terminals are in an unused state, and the corresponding external pins P
1
, P
3
, P
4
, P
6
and P
9
, P
11
, P
12
, P
14
of the package are designated as NC pins. In this case, in accordance with the approach that control signals control each 8-bit data input-output terminal group, the first strobe signal terminal STB
0
and the first mask signal terminal MSK
0
are in an unused state, so that only the second strobe signal terminal STB
1
and second mask signal terminal MSK
1
are in a used state, and the second strobe signal STB
1
and second mask signal terminal MSK
1
are supplied to the input-output buffer circuits and write amplifier corresponding to the used 8-bit data input-output terminal group.
To describe the strobe signals, a first switch SW
0
in the strobe signal supply lines
10
and
20
is controlled to a non-conductive state, while a second switch SW
1
is controlled to a conductive state, so that the second strobe signal STB
1
is supplied to the eight input-output buffer circuits IO-BUF that are in use. The mask signal MSK
1
is also supplied to the write amplifiers WA
0
to WA
7
and WA
8
to WA
15
on both sides by a similar switching circuit.
In the case of the 4-bit configuration shown in
FIG. 3
, as is indicated by the bonding wires
3
, only the two bits DQ
2
and DQ
5
are used from the first data input-output terminal group DQ
0
to DQ
7
, and only the two bits DQ
10
and DQ
13
are used from the second data input-output terminal group DQ
8
to DQ
15
. The other data input-output terminals are in an unused state. Furthermore, the first strobe signal terminal STB
0
and mask signal terminal MSK
0
are also in an unused state, so that the second strobe signal STB
1
and mask signal MSK
1
are supplied in common to the input-output buffer circuits and write amplifier corresponding to the data input-output signals of the abovementioned four bits.
Thus, switching is performed in accordance with the data input-output terminal configuration so that control signals such as strobe signals, mask signals and the like for the data input-output signals are used in common for data input-output signals in word units (8-bit units). As a result, the circuit corresponding to the first data input-output terminal group

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