Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2001-11-21
2003-04-22
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S056000, C326S080000
Reexamination Certificate
active
06552568
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a circuit for level adjustment on the output side between a programmable, large-scale integrated component having low signal voltage and a microprocessor system having high signal voltage.
2. Description of the Prior Art
The ongoing development of semiconductor technology in terms of functionality, circuit speed, and circuit density has led to constant reduction in the supply and signal voltages.
Since large-scale integrated semiconductor components having differing supply and signal voltages are used in electronic circuits on printed circuit boards, it is essential to provide for a level adjustment of the signals that assures the connection of these LSI semiconductor components. If a circuit includes only example CMOS level 5 V, it is not necessary to provide for level adjustment.
By way of example, if the output signals from an FPGA (Field Programmable Gate Array), which has a 3.3 V power supply because of its circuit density, are connected to a component having a 5 V power supply and CMOS input level, the output signals will not be recognized by the CMOS″ component unless means for level adjustment are provided. The FPGA generates the “1” state with, for example, 2.4 V, but confident “1” recognition by the CMOS component may be set at 4.2 V. The signal level must therefore be adjusted so that the signal level for the “1” state is raised above the input threshold for recognition of the “1” state by the CMOS component.
An open drain output with pullup resistor, as described in “The Programmable Logic Data Book”, Xilinx, 1999 may be used to this end. Another description of an open drain output is included in “High-Speed CMOS logic Data”, Motorola, 1988. This output only switches the output to ground in the “0” state. In the “1” state, the output is highly resistive, so that only the pullup resistor that is connected to the higher line voltage raises the signal line to the higher signal level. This arrangement has the critical disadvantage, however, that the response time in large resistors is significant. In order to shorten the response time, the pullup resistor must be made smaller, which itself entails the disadvantage of increased current consumption in the “0” state. For example, when its output is switched to “0”, a 1000 Ohm pullup resistor draws 5 mA signal current. When a large number of level-adjusted signals are involved, the total drawn signal current is accordingly very large.
If a pullup resistor is wired to a true push-pull output in an integrated circuit that has low supply voltage, depending on the push-pull output's internal configuration, an undesirable cross-current may be created. This cross-current is caused by the resistive value of the pullup resistor and the potential difference between the first lower supply voltage and the second higher supply voltage. In particularly extreme cases, the cross-current can destroy the push-pull output. One reliable method for adjusting signal levels that also gives fast switching speeds is provided by the use of a levelshifter component, which is described in the datasheet “SN54CBTD3384, SN74CBTD3384 10-Bit FET Bus Switches with Level Shifting”, published in 1995 by Texas Instruments and revised in 1998. The output from the component with low signal voltage is coupled to the levelshift component's input. The levelshifter component's output is in turn coupled to the input of the component with high signal voltage. The critical disadvantage of this arrangement is that one or more levelshifter components must also be integrated into the circuit as a whole, thus taking up additional space on the printed circuit board and having the effect of increasing the cost of the electronic circuit on the printed circuit board. The circuit for level adjustment that is described in DE 196 44 772 C2, and which is designed to be inexpensive, also suffers from the disadvantage that 4 resistors and two bipolar transistors are required for each signal to be converted. In wide, parallel, level-adjusted system buses a large number of stand-alone components are needed, which increase the space requirement on the printed circuit board for the electronic circuit and entail greater assembly effort during manufacture. In addition, the possible signal distortion and signal load of this level adjustment as described in DE 196 44 772 C2 is not acceptable for rapid parallel system buses. If its use is restricted exclusively to the purpose described in DE 196 44 772 C2 of coupling two integrated circuits having different signal voltages by means of a 12C bus with just a small number of signals, the inexpensive transistor circuit described in DE 196 44 772 C2 is indeed adequate, but with a large number of signals requiring level adjustments, this arrangement is too cumbersome and thus disadvantageous.
A bidirectional voltage converter is known from patent document FR 2 748 359 B1, according to which the voltage levels are generated by means of pullup resistors. The voltage converter described in FR 2 748 359 B1 does not require any control signals to determine the data direction. In this case, the fact that a latch with bidirectional effect and the pullup resistors have to be integrated may be considered disadvantageous. A voltage converter for level adjustment of this kind can only be included in a programmable, large-scale integrated FPGA component as a supplementary measure.
SUMMARY OF THE INVENTION
The object of the invention is to provide an inexpensive, space-saving level device for adjusting levels between a programmable, large-scale integrated FPGA component having low signal voltage and a microprocessor system having high signal voltage.
The level adjusting device must consist of a very few, small components, or none at all because of the limited space available. At the same time, the use of commercially available integrated components should be avoided for reasons of cost.
The object is resolved according to the invention by a pullup resistor that is connected to the output of a programmable, large-scale integrated FPGA component having low signal voltage. Internally, the internal output signal is digitally combined with the output signal in feedback from the output path, such that for a signal state change from “0” to “1” the output level of the signal is the active driver up to the value “1” of the low signal voltage, and when the “1” state is reached, the output driver is switched to high resistance (tri-state) for the low output level, so that only the pullup resistor is in effect for increasing the level to the high signal level. Consequently, the pullup resistor is not involved for the entire signal gain, but is only active for the remaining difference between the low signal level of the output driver and “1” threshold value of the input having high signal level. The slow build-up time that characterizes an open drain circuit is shortened in this application to a period that is sufficient for this function. The pullup resistor is capable of receiving a value from twice to four times as high as is possible in a purely open drain wiring, which serves to keep power loading due to signal currents low.
The circuit for level adjustment according to the invention is also capable of functioning in conjunction with programmable, large-scale integrated components having a signal voltage of 2.5 V. This entails a slightly longer build-up time for the signal, because the signal level that must be increased by the pullup resistor is greater.
The invention will be described in the following with reference to an exemplary embodiment thereof and the associated figures.
REFERENCES:
patent: 5568062 (1996-10-01), Kaplinsky
patent: 5680063 (1997-10-01), Ludwig et al.
patent: 5726590 (1998-03-01), Isono
patent: 6028447 (2000-02-01), Andrews
patent: 6114884 (2000-09-01), Kaplinsky
patent: 196 44 772 (1996-10-01), None
patent: 196 44 772 (1998-05-01), None
patent: 533340-A2 (1993-03-01), None
patent: 92307286 (1993-03-01), None
patent: 0616430-A2 (1994-06-01),
Baxley Charles E.
Chang Daniel
Phoenix Contact GmbH & Co. KG
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