Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-01-15
2003-09-09
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S631000, C438S633000, C438S692000, C438S697000, C438S699000, C438S723000, C438S724000, C438S725000, C438S782000, C438S786000, C438S787000, C438S791000
Reexamination Certificate
active
06617241
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the general field of integrated circuits with particular reference to planarizing uneven surfaces, more specifically to surface films greater than about one micron thick.
BACKGROUND OF THE INVENTION
Global planarization of insulating layers formed over depressions and raised portions on a surface can be done by block resist and resist etch back, block resist and spin on glass, and chemical-mechanical polish. Of these chemical-mechanical polish (CMP) gives the highest global planar surface and is now widely used. CMP has been refined over the years in terms of process, equipment, and slurries. In U.S. Pat. No. 5,015,602, Van Der Plas et al. show a method of forming reverse image photoresist over low spots on an insulating surface. The insulating layer is etched and then planarized using CMP. U.S. Pat. No. 4,954,459 (“Method of Planarization of Topologies in Integrated Circuit Structures”) and U.S. Pat. No. 6,025,270 (“Planarization Process using Tailored Etchback and CMP”) describe other variations of similar concepts. Applying the methods disclosed in these patents does result in improved surface smoothness but these methods are all limited to planarization of dielectric layers having thickness of 1 micron or less.
The dielectric films used in the fields of sensors and optical communications can be much thicker. For instance, in the optical communication field, optical waveguides using a silicon-based dielectric can have a thickness ranging from 1 to 10 microns. Patterning and planarizing such thick dielectric layers presents a different set of problems. For example, as shown in
FIG. 1
, a dielectric layer
11
has been deposited over a base substrate
12
. Elevated peak areas
13
(typically wires), of height h (typically about 6 microns, are separated by gaps, or valleys,
14
, with layer
11
being both thick and approximately conformal.
Microstructures of this thickness make it difficult for a thick conformal dielectric layer to be over-laid so that a desired surface conformity is obtained and the gap is completely filled with another dielectric material. To achieve this, various known deposition methods may be used. These methods include plasma-enhance chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atmospheric-pressure chemical vapor deposition (APCVD), and high-density plasma chemical vapor deposition (HDPCVD). Other deposition methods, which are found more in the research labs, are photon-induced CVD, microwave electron cyclotron resonance CVD, microwave plasma-assisted CVD.
Among the more conventional CVDs, APCVD, HPDCVD and PECVD have fast deposition rate, low deposition temperature, and somewhat conformal step coverage. LPCVD, on the other hand, gives good conformal step coverage but has low deposition rate and high deposition temperature. Conformal step coverage is coverage in which equal film thicknesses exist over all substrate topography regardless of its slope. Another popular method is flame hydrolysis deposition (FHD). However, when using these methods to deposit a thick layer of dielectric material, hereinafter referred to as an oxide layer, especially by PECVD, HPDCVD, and LPCVD, two distinct features are inherent.
The first feature is shown in
FIG. 1
, in which the oxide deposited over the microstructures has a cross-sectional trapezoidal structure with downwardly tapering sides and rounded corners. In this instance, the sloping sides of the sidewalls have an angle greater than 90 degrees. It is also possible for the oxide deposited over the microstructures, while still having a trapezoidal cross-section, to have upwardly tapering sides so that the angle &thgr; of the two sidewalls is less than 90 degrees. Using PECVD or LPCVD is more likely to yield a covering similar to that shown in
FIG. 1
while using HDPCVD tends to yield coverage that where the angle is less than 90°. These features make the successful planarization of thick deposited materials difficult when conventional prior art approaches to etching and CMP are used.
After the thick conformal oxide layer has been deposited, the next step is to remove the oxide deposited over the microstructures (i.e. the peaked or raised portions of layer
11
) so that a planar surface is obtained. The etching process can be either reactive ion etching (RIE) or inductively coupled plasma (ICP) using a mask that is the reverse of the mask that generated the microstructures. Preceding the etching process is the lithography patterning process. This process consists of photoresist coating, pre-bake, exposing according to the mask layout, an optional post exposure bake, and finally developing with or without an optional final hard bake. Photoresist layer
21
is applied, using a spin-on method, to cover the entire oxide layer
11
as shown in FIG.
2
.
Due to the large and steep step heights involved, it is difficult to ensure a consistent thickness of the photoresist coating over the full surface of layer
11
. The photoresist layer portions over the raised portions of the oxide layer are thinner than the photoresist layer portion in the valleys. For a typical 1 micron photoresist, the photoresist in the valleys is typically 1-about 9,000 Angstroms thicker than that collected at the raised portions. This depends on the severity of the topography and the coating conditions, (particularly spin speed).
After exposing the photoresist through the reverse mask, the thinner coat of photoresist material is then removed. When applying the negative mask, positive and negative bias of the reverse mask can be used. Positive bias will increase the exposing area, i.e. the exposing width is larger than the width of the microstructures. Negative bias will decrease the exposing area, i.e. the exposing width is larger than the width of the microstructures. Note that there are limitations to the amount of bias that can be be applied and disadvantages of microstructures layout, i.e. the spacing between the microstructures.
FIG. 3
shows the structure after patterning with light pattern
31
.
Due to differences in resist thickness on the peaks (very thin) and in the valleys (very thick), etching proceeds not only in a downward direction but also extends sideways resulting in a cross section as shown in FIG.
4
. The remains of the original raised portions now looks very much like horns
41
that extend upwards from the surface of layer
11
. If, now, the remaining photoresist is removed and CMP is performed, the horn-like structures
41
tend to break off, causing undesirable dishing
51
in the surface as shown in FIG.
5
. This is because the proximal ends of the horn-like structures experience high torsional forces in response to the polishing forces applied to the distal ends of the horn-like structures during CMP. Additionally, the breakaway horn-like structures may get mixed in with the slurry, becoming, in effect, polishing agents. This is undesirable as these horn-like structures are too coarse so they damage the polished surface. Additionally, the breakaway horns can get embedded in the CMP pad which leads to scratching of the surface being polished.
Thus, there exists a need for an efficient and cost effective method to planarize thick layers so as to provide a smooth planar surface.
SUMMARY OF THE INVENTION
It has been an object of at least one embodiment of the present invention to provide a process for chemical mechanical polishing of thick layers having uneven top surfaces made up of peaks and valleys.
Another object of at least one embodiment of the present invention has been that it be applicable to both positively and negatively sloping valley sidewalls.
Still another object of at least one embodiment of the present invention has been that it not require the creation of any new masks.
These objects have been achieved by means of a process that, in its first embodiment, initially allows the formation of ‘horns’ in the surface that is to be planarized. Said horns are then selectively etched away while other parts of the surface are prot
Ackerman Stephen B.
Gurley Lynne
Institute of Microelectronics
Niebling John F.
Saile George O.
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