Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-27
2003-07-08
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S299000
Reexamination Certificate
active
06590247
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a MOS capacitor with wide voltage and frequency operating ranges.
2. Discussion of the Related Art
In the field of integrated circuits, integrated MOS capacitors are commonly used.
For example, in EPROM, EEPROM and Flash EPROM integrated circuits MOS capacitors are employed for integrating charge pumps for boosting the supply voltage. The use of MOS capacitors is common especially in the field of Flash EPROM devices, where there is a trend towards using devices having a single power supply, possibly with values lower than 3 V. In Flash EPROM devices, it is necessary to internally boost the voltage supply to generate voltages for read, programming and erasing operations.
To this end, integrated capacitors having different capacitances and operating in different biasing conditions are commonly provided.
Known MOS capacitors are substantially of two types: N-well (or P-well) capacitors, and PMOS (or NMOS) capacitors.
An N-well capacitor comprises an N type well formed in a P type substrate, with an insulated gate superimposed over the N type well and an N+ contact region inside the N type well. Essentially, an N-well capacitor is a P-channel MOSFET without source and drain diffusions. The electrodes of the capacitor are respectively formed by the insulated gate and the N type well. As is known, the capacitance is a function of the voltage applied to the gate. There are two gate voltage ranges wherein the capacitance value is acceptable, that is, for gate to N-well voltages lower than the threshold voltage (the gate voltage that causes an inversion layer to be formed in the N type well under the insulated gate) and for gate to N-well voltages higher than the so-called flat-band voltage (that is, in the so-called accumulation operating region). For gate voltages between these two ranges, that is, in the so-called depletion region, the capacitance value is approximately one half or one third the capacitance in accumulation and inversion operating regions. Furthermore, the N-well capacitor can operate in inversion region only for low frequencies, because the formation of the inversion layer, being due to generation-recombination processes, is slow. In conclusion, the N-well capacitor works sufficiently well only in the accumulation region, that is, for gate voltages sufficiently positive.
Similar consideration hold true for a P-well capacitor, which is the dual counterpart of the previously described N-well capacitor, with N type regions and P type regions interchanged.
A PMOS capacitor comprises an N type well formed in a P type substrate with at least one P+ diffused region inside the N type well, an insulated gate superimposed over the N-type well, and an N+ contact region to the N type well. The two terminals of the capacitor are the insulated gate and the P+ diffusion; the N type well is biased at a constant potential (generally the most positive voltage inside the chip) suitable to keep the N well/P substrate junction reverse biased. Due to the presence of the P+ region, the inversion region can be reached quite fast, but it is not possible to operate the capacitor in the accumulation region (because the terminals of the capacitor do not comprise the N type well). Consequently, this capacitor has a sufficiently high capacitance only in the inversion region, that is, for gate voltages sufficiently negative.
Similar consideration hold true for an NMOS capacitor, which is again the dual counterpart of the PMOS capacitor with N type regions and P type regions interchanged.
From the above considerations, it follows that N-well capacitors can only be used for positive charge pumps (and similarly P-well capacitors can only be used for negative charge pumps), while PMOS capacitors can only be used for negative charge pumps (and NMOS capacitors can only be used for positive charge pumps).
In view of the state of the art described, it is an object of the present invention to provide a MOS capacitor structure having as far as possible an “ideal” behavior, that is, a capacitor having substantially the same capacitance for any voltage applied across it and for any frequency variation of this voltage.
SUMMARY OF THE INVENTION
According to one embodiment of the present invention, these and other objects are achieved by a MOS capacitor comprising a semiconductor substrate, a first well region of a first conductivity type formed in said substrate, at least one first doped region formed in said first well region, and an insulated gate layer insulatively disposed over a surface of the first well region, the at least one first doped region and the insulated gate layer respectively forming a first and a second electrode of the capacitor, characterized in that the first well region is electrically connected to the at least one first doped region to be at a same electrical potential of the first electrode of the capacitor.
In another embodiment of the invention, the at least one first doped region includes a plurality of spaced-apart doped regions, and the insulated gate layer is insulatively disposed over the whole surface of the first well region.
In another embodiment of the invention, the MOS capacitor comprises a first contact doped region of the first conductivity type formed in the first well region for biasing the first well region, the first contact doped region being electrically connected to the first doped regions. Further, the semiconductor substrate can be of the second conductivity type or of the first conductivity type.
In the latter case, the MOS capacitor can further comprise a second well region of the second conductivity type formed in the semiconductor substrate and containing the first well region. A second doped contact region of the second conductivity type is in this case formed in the second well region for biasing the second well region at a potential suitable for isolating the first well region from the semiconductor substrate.
In another embodiment of the invention, the insulated gate layer also extends over a surface of the second well region, and at least a second doped region of the second conductivity type is formed in the second well region and is electrically connected to the first doped region and to the first doped contact region inside the first well region.
In another embodiment of the invention, the MOS capacitor further comprises at least a third doped region of the first conductivity type formed in the second well region and electrically connected to the first and second doped regions and to the first doped contact region.
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patent: 3612964 (1971-10-01), Kawazu
patent: 4001869 (1977-01-01), Brown
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patent: 5673232 (1997-09-01), Furutani
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European Search Report from European Patent Application 96 830420.4, filed Jul. 30, 1996.
Patent Abstracts of Japan, vol. 16, No. 360 (E-1243), Aug. 4, 1992 & JP-A-04 112564 (NEC IC Microcomput. Syst. Ltd.), Apr. 14, 1992.
Patent Abstracts of Japan, vol. 7, No. 280 (E-216), Dec. 14, 1983 & JP-A-58 159367 (Matsushita Denshi Kogyo KK) Sep. 21, 1983.
Ghezzi Stefano
Ghilardelli Andrea
Golla Carla Maria
Dickey Thomas L
Morris James H.
SGS--Thomson Microelectronics S.r.l.
Tran Minh Loan
Wolf Greenfield & Sacks P.C.
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