Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-08-11
2003-05-06
Nguyen, Cuong Quang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06559494
ABSTRACT:
TECHNICAL FIELD
This invention relates to a semiconductor device and a method for fabricating the semiconductor device, which is particularly suitable for fabricating a semiconductor memory device.
More particularly, this invention relates to a structure of a semiconductor device and a method for fabricating such a semiconductor device, which is obtained by utilizing a self aligned contact (SAC) technique for forming a contact hole above each active region of the semiconductor device. A DRAM device or the like obtained by this invention shows little or no degradation of data retention characteristics.
BACKGROUND ART
A method of fabricating a DRAM according to a design rule of approximately 3 &mgr;m is described as an example in order to illustrate a conventional method of fabricating a semiconductor device using the SAC technique.
FIGS. 21
to
40
are, respectively, sectional views for illustrating a conventional method of fabricating a DRAM.
Reference is now made to FIG.
21
. Initially, a silicon semiconductor substrate
1
is entirely formed with an approximately 100 angstroms thick silicon thermal oxidation film
2
thereon by thermal oxidation, which is followed by further deposition of an approximately 500 angstroms thick silicon nitride film
3
by CVD. Subsequently, using photomechanical and etching techniques, the silicon nitride film
3
is selectively left only in regions wherein an element is to be formed.
Referring to
FIG. 22
, a thermal oxidation film
4
is selectively formed between the nitride films
3
with a thickness of approximately 3000 angstroms by thermal oxidation to provide an element separation oxide film, which is followed by removal of the nitride films
3
to form an element-forming region. In the figure, the left-side half indicates a memory cell portion A and the right-side half indicates a peripheral circuit portion B.
Next, a thermal oxidation film
5
which serves as a gate oxide film of a transistor is formed with a thickness of approximately 90 angstroms by thermal oxidation. Thereafter, phosphorus-doped polysilicon film
6
wherein phosphorus (P) is doped at a concentration of approximately 5×10
20
atoms/cm
3
, and tungsten silicide film (WSi
2
)
7
are, respectively, deposited with a thickness of approximately 500 angstroms by CVD to form a double-layered film
8
(which may be hereinafter referred to simply as a polyside).
Further, a silicon nitride film
27
is formed with a thickness of approximately 1000 angstroms by CVD. The silicon nitride film
27
serves as an etching mask at the time of the formation of a polyside gate and also as a stopper at the time of making holes for SAC. It will be noted that in
FIGS. 22
to
40
, the reference numeral
1
indicating the semiconductor substrate is, for convenience, not shown.
In
FIG. 23
, the nitride film
27
is subjected to photomechanical and anisotropic etching to leave desired portions of the nitride film
27
in a pattern. The polyside film
8
is anisotropically etched through the pattern of the nitride film
27
to form gate electrodes
8
with a gate length of approximately 0.3 &mgr;m. The polyside film
8
is etched to extend just above the gate oxide film
5
as shown.
Subsequently, phosphorus ions are self-alignedly implanted into the respective gate electrodes
8
and the element separation oxide films
4
at a concentration of approximately 1×10
13
atoms/cm2 by an ion implantation, thereby forming lightly doped source/drain regions of a MOS transistor, i.e. so-called n-source/drain regions
10
a
,
10
b
,
10
c
and
10
d
. In the figure, the source/drain region
10
a
is connected with a bit line through a contact hole in a subsequent step, and the source/drain region
10
b
is connected with a lower electrode of a capacitor through another contact hole in a subsequent step.
Referring to
FIG. 24
, a silicon nitride film
11
is deposited with a thickness of approximately 800 angstroms by CVD. The nitride film
11
serves as side walls of a transistor having an LDD structure.
In
FIG. 25
, the silicon nitride film
11
is anisotropically etched to leave side walls
11
a
of the nitride film at the side walls of each gate electrode
8
. The width, W
1
, of the side wall
11
a
is approximately 800 angstroms. It should be noted that the thin gate oxide film
5
does not act as a stopper for the anisotropic etching of the nitride film, but is readily removed by over-etching, thereby causing the source/drain regions
10
a
,
10
b
to be exposed.
In
FIG. 26
, the memory cell portion A is covered with a resist
12
according to a photomechanical technique. Using ion implantation, the gate electrode
8
, the element separation oxide film
4
and the side walls
11
a
of the nitride film are self-alignedly implanted with arsenic at a concentration of approximately 5×10
15
atoms/cm2, respectively, thereby forming a heavily doped source/drain region, i.e. a so-called n+ source/drain region
13
, of the MOS transistor.
At that time, the memory cell portion A has been covered with the resist
12
, so that such an n+ source/drain region as mentioned above is prevented from being formed in the memory cell portion A. In the event that the n+ source/drain region is formed in the memory cell portion A, junction leakage current increases to degrade data retention characteristics. Accordingly, only the lightly doped n− source/drain regions are formed in the memory cell portion A.
In
FIG. 27
, the resist
12
is removed from the memory cell portion A, and an oxide film containing boron and phosphorus (hereinafter referred to simply as BPSG) is deposited with a thickness of approximately 4000 angstroms by CVD, thereby forming an interlayer insulating film
14
.
It should be noted here that in the above case, it is not appropriate to use an oxide film which is free of any boron or phosphorus, e.g. an TEOS oxide film. This is because an oxide film free of boron or phosphorus exhibits only a small selection ratio relative to the nitride film used as an etching stopper at the time of making a hole for SAC.
Referring to
FIG. 28
, the thermal treatment is carried out in an atmosphere of nitrogen at approximately 850° C. for 20 minutes, by which the BPSG is thermally sagged to make the layer insulating film
14
flat on the surface thereof. At that time, the oxide film
14
at a portion where SAC is to be formed between the gate electrodes
8
has a thickness, t
1
, of approximately 6000 angstroms.
In
FIG. 29
, bit line contact holes
15
each having a diameter of approximately 0.3 &mgr;m are, respectively, formed above the source/drain
10
a
of the memory cell portion A and the source/drain region
10
c
of the peripheral circuit portion B according to photomechanical and anisotropic oxide film-dry etching techniques. Each hole
15
is formed to connect a bit line and an active region therewith. At the time of the formation of the contact holes
15
, the BPSG is over-etched by 30% which corresponds to a thickness of 9000 angstroms of the BPSG. Because the etching rate of the nitride film is about {fraction (1/20)} of that of BPSG, the nitride film
27
located above the source/drain region
10
a
of the memory cell portion is etched by a thickness, t
2
, of approximately 250 angstroms.
In
FIG. 30
, as in the case of the gate electrodes
8
, a polyside layer
18
composed of a phosphorus-doped polysilicon film
16
and a tungsten silicide (WSi
2
) film
17
is deposited by CVD to fill the bit line contact hole therewith, followed by formation of a desired pattern by photomechanical and anisotropic dry etching techniques to form polyside interconnections
18
. The line width, W
2
, of the polyside interconnection
18
is in the range of approximately 0.3 to 0.5 &mgr;m, and the interconnections serve as a bit line of a DRAM and are, respectively, connected via the bit line contact holes
15
to the source/drain regions
10
a
,
10
c.
In
FIG. 31
, an approximately 3000 angstroms thick silicon oxide film is deposited over the substrate by CVD to form
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Cuong Quang
LandOfFree
Semiconductor device and a method for fabricating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and a method for fabricating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and a method for fabricating the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3078332