Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-08-31
2003-04-08
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S082000, C438S099000, C438S707000, C438S780000, C438S781000, C438S788000, C257S040000, C430S311000, C430S313000
Reexamination Certificate
active
06544902
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the formation of patterns for resists and other protective materials employed on semiconductor devices. More specifically, the present invention relates to a method for forming patterns in a resist or other protective material by traversing an energy beam thereover instead of exposing the material to radiant energy through a mask.
2. State of the Art
The manufacture of semiconductor devices routinely involves multiple masking steps. For example, resist material, also commonly termed “photo resist” material due to its light sensitivity, is deposited on a semiconductor substrate and patterned by exposing a portion of the resist material to ultraviolet light through a mask which defines a positive or negative resist pattern. In the case of a positive resist pattern, the exposed resist material is chemically modified and/or degraded by the ultraviolet light such that the exposed resist material portions may be removed by conventional developing techniques as known in the art. In the case of a negative resist pattern, the exposed resist material is chemically modified to harden or set by exposure to the ultraviolet light such that the exposed resist material portions are not degraded by conventional developing techniques, but instead the unexposed resist material may be removed by developing, resulting in a resist pattern on the semiconductor matching the mask pattern. Suitable additional procedures, such as deposition, etching, or the like, are carried out after the resist is patterned to form desired features of a semiconductor device. The resist material is then removed, leaving the desired semiconductor features, and manufacturing continues. The masking process may be repeated as desired with differently patterned masks in conjunction with associated material deposition and removal steps until all of the desired features of the semiconductor have been formed.
FIGS. 1 and 2
illustrate an exemplary process of creating a resist pattern on a semiconductor device.
FIG. 1
illustrates a semiconductor device
100
covered by a layer of resist material
110
. A mask
120
having both radiation-transparent portions
122
and radiation-opaque portions
124
is aligned over the resist material
110
. Electromagnetic radiation
130
(such as ultraviolet light, x-rays or visible light) is directed perpendicularly toward the mask
120
and passes through the transparent portions
122
of the mask
120
to be absorbed by the resist material
110
. Those portions of the electromagnetic radiation
130
meeting the opaque portions
124
of the mask
120
are either reflected or absorbed by the material of mask
120
. The resist material
110
exposed to the electromagnetic radiation
130
through transparent portions
122
of mask
120
undergoes a chemical change, as previously discussed above (depending upon whether the resist is of the positive or negative type), to define a pattern including resist features
140
as illustrated in FIG.
2
.
The miniaturization of semiconductor devices requires the definition of higher resolution resist patterns having smaller dimensional tolerances and variances. With increasing frequency, the masking processes currently available are being replaced with processes which provide superior resolution and miniaturization of the resist patterns. For example, a dual mask process is disclosed in U.S. Pat. No. 5,851,734 to Pierrat, wherein the use of two masks during a masking process produces better resolution of a desired resist feature than can be accomplished with one mask. In Pierrat, a first resist portion is exposed by a first mask which is used to define one edge of a desired resist feature. A second mask defines the second edge of the desired resist feature. In a positive mask, only that portion of the resist material exposed by both the first and the second mask remains following etching. Similarly, in negative masking, that portion of the resist material which is exposed by both the first and the second mask is removed from the resist layer. This masking technique provides a method whereby smaller resist features can be formed.
In addition to the use of masking processes as described above to create resist patterns for definition of semiconductor device features, masking processes may also be employed to form a layer of protective material over portions of die locations on a semiconductor wafer. For example, a protective material may be deposited in a selected pattern over wire bonds or conductive traces to protect such features from damage or unwanted coating during a particular stage of processing, handling or testing. A portion of a protective material layer covering a semiconductor wafer is exposed, for example, to ultraviolet light through a mask defining the desired protective pattern. The exposed or unexposed portion of the protective material (depending upon its chemical makeup) is then developed and washed from the semiconductor wafer, leaving a pattern of material adhered to the wafer protecting selected locations.
In addition to the trend toward increased miniaturization, another significant consideration in semiconductor device fabrication is process speed. Significant economic advantages may be realized when the rate of production of semiconductor devices fabricated during a given time period is increased. Conventional masking processes require a series of steps including the application of a resist material to a semiconductor substrate such as a wafer, alignment of a mask over the active surface of the wafer, exposure of the resist material to appropriate wavelength radiation through at least one mask to define a desired pattern on the resist, developing of the resist material and rinsing of the excess resist material from the semiconductor wafer. Elimination of a single step in the resist patterning sequence would save substantial time and boost production rates. If the masking step were to be eliminated, not only process time but also the considerable expense of the mask itself would be saved. If the development step were to be eliminated, even further production efficiencies would be realized.
In addition to the cost and relatively slow speed involved in mask placement and alignment, conventional masking of resist material must be effectuated on an entire semiconductor substrate including hundreds or thousands of semiconductor die locations separated by so-called “streets” before the dice are singulated therealong. Thus, alignment must be accurate across an entire substrate such as a wafer, which is proving to be increasingly difficult as feature dimensions shrink, wafers become larger as technology advances (the next generation wafers in development are 30 cm in diameter) and non-planarity of wafer surfaces across the larger wafers becomes more significant to the fabrication process.
The use of lasers in selected aspects of semiconductor fabrication is becoming more common. One use of lasers in semiconductor fabrication is for the marking of a semiconductor package with part numbers, serial numbers, or other information. Laser marking techniques are desirable because of the enhanced efficiency, accuracy and speed of laser marking. The beams of such marking lasers are controlled, manipulated, and triggered to mark the semiconductor only in a specified or programed pattern of indicia. U.S. Pat. No. 5,838,361 to Corbett and U.S. Pat. No. 5,937,270 to Canella each describe exemplary apparatus, methods and techniques used in laser marking of semiconductor chips. The disclosure of each of the Corbett and Canella patents is hereby incorporated herein by reference.
Lasers are also employed in stereolithographic processes used to form layered structures by selectively exposing portions of a photopolymer film to ultraviolet wavelength laser radiation, as disclosed in more detail in the aforementioned U.S. patent applications Ser. Nos. 09/259,142 and 09/259,143. Such processes have been specifically adapted and improved for use in certain aspects of
Lee Jr. Granvill D
Micro)n Technology, Inc.
Smith Matthew
TraskBritt
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