Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-23
2003-04-22
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S355000, C257S371000, C257S392000, C257S393000, C257S544000
Reexamination Certificate
active
06552397
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to charge pumps, and more particularly, to a charge pump formed on a silicon-on-insulator substrate.
BACKGROUND OF THE INVENTION
A prior art charge pump formed using MOS technology is shown in FIG.
1
A. An n-channel MOS transistor with a diode configuration (i.e. drain and gate shorted with body grounded) serves as a diode. The voltage drop of the “diode” (also referred to as “turn-on” voltage) is simply the transistor threshold voltage (V
t
) with body bias of source side. Although an ideal V
t
of the n-MOS should be 0 volts, native n-channel transistors (i.e. transistor without V
t
implant as in typical transistors) are used in practical charge pump circuits. As seen in
FIG. 1C
, the clock (&phgr;
1
) pumps charge to the output node A and boosts it's potential higher than the clock by (V
cc
−V
t
). This charge pump can be used as word-line driver in DRAM or flash memory.
FIG. 1B
shows that the equivalent circuit of such a charge pump building block is a diode (with turn-on voltage V
t
) connected to a capacitor. Typically the capacitance (C
pump
) is much larger than other stray capacitances at node A, so that the full pulse height can be “pumped” to node A.
A prior art 2-phase two stage charge pump circuit is shown in
FIG. 2A
by using 2 building blocks and pumped by 2 non-overlap clocks. The voltage waveform at node A is still a boosted level of the clock &PHgr;
1
by (V
cc
−V
t
) as illustrated in FIG.
1
. As seen in
FIG. 2C
, as the first clock &phgr;
1
pulses high, transistor N
1
is off and N
2
is on, thus node B is charged to (2V
cc
−V
t
). As &phgr;
1
is pulsing down, N
2
is off. As &phgr;
2
is pulsing up (shortly after &phgr;
1
pulsing down due to the nature of non-overlap clocks), node B reaches (3V
cc
−2V
t
). After this initial cycle, the voltage waveform at node B follows clock &phgr;
2
with boosted levels and between boosted levels by 2(V
cc
−V
t
), i.e. oscillating in between 2(V
cc
−V
t
) and V
cc
+2(V
cc
−V
t
) The equivalent circuit diagram of
FIG. 2A
is shown in FIG.
2
B.
The illustration above is a simplified case when the output current load is negligible. In real circuit applications, the output of a charge pump circuit may need to drive other circuits with boosted stable DC level. A realistic charge pump may need many stages of charge pump with large enough (pumping) capacitors as well as an output rectifier. Such a charge pump is shown in
FIG. 3A
, which is a two-phase multi stage charge pump.
FIG. 3B
shows the timing diagram for the 2 phase non-overlap clock signals input to the charge pump. The output rectifier typically consist of capacitors and resistors (not shown in FIG.
3
A). The driving capability of the charge pump depends on several characteristics of the devices, such as transistor size, V
t
, the magnitude of capacitance, clocking pulse height and frequency, and the number of charge pumping stages. The output rectifier serves to maintain a stable DC level for load circuits. The output voltage can be boosted to a high voltage level, which is limited by junction breakdown.
The implementation of such charge pumping circuits of
FIGS. 1
,
2
, and
3
by CMOS technology is well known. The n-channel transistors in the charge pump needs to sustain high voltage across the gate oxide and source/drain junctions and also need a low enough threshold voltage (V
t
) for minimizing the “diode” drop during operation. Native n-channel transistors (i.e. transistor without V
t
implant as required in typical transistors) are used in practical charge pump circuits. The “pumping” capacitor is typically large in area and implemented by a poly-to-poly structure with dielectric thickness of 300A to 500A or metal-to-metal with a thicker dielectric (~1000A to 2000A). A typical charge pump circuit implemented on VLSI is relatively large due mainly to the large capacitor area required for pumping enough charge to supply the load current (e.g. several hundreds of mA) to high-voltage circuits.
Integrated circuits fabricated on silicon-on-insulator (SOI) wafers is useful for applications in high speed, low power, and high voltage. A direct implementation of the CMOS charge pumps described above is very difficult, especially on SOI wafers with a thin silicon layer (for fully depleted transistors). First, the body of each transistor is not grounded and is left floating. The leakage current in a transistor with floating body is large during off-state due to the parasitic npn bipolar transistor (i.e. n+-source, p-body, and n+-drain) with the floating body as base. This leakage current will degrade the efficiency of the charge pump significantly.
REFERENCES:
patent: 6040610 (2000-03-01), Noguchi et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Taiwan Semiconductor Manufacturing Co. Ltd.
Wojciechowicz Edward
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