Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-05-24
2003-05-27
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S036000
Reexamination Certificate
active
06571347
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention pertains in general to an apparatus for storing a computer initiation program and, more particularly, to an apparatus and method for computer initiation program recovery.
2. Description of the Related Art
A computer initiation program, most commonly known as a BIOS program, provides an essential and indispensable function during the initial or “boot-up” process of a computer. To prevent the program from being edited, over-written, or otherwise altered, the program has traditionally been stored in a read-only-memory (“ROM”). Recently, vendors have started to store BIOS programs in flash memories, a type of non-volatile memory that permit its contents to be reprogrammed electrically by anyone without having to remove the memory from the motherboard. By storing a BIOS program in a flash memory, the vendors allow users of the program to directly update the BIOS program or correct existing “bugs” in the program by, for example, posting new or updated programs on the Internet so that they may be downloaded by the users. Such an alternative may be economical compared to having to replace at least the ROM in which an outdated or defective BIOS program is stored.
Although storing the BIOS program in a flash memory may provide some convenience to users and vendors alike, unintended results may occur which may be fatal to computer operations, such as incorrect storage of a new or updated BIOS program or incomplete storage of the BIOS program due to power outage during the “burn-in” process. A computer virus may also infect the BIOS program. Each of these occurrences renders the computer system unable to function. Although the computer system may be initiated by using a BIOS program stored on a floppy disk, this remedy may not be immediately available, such as if a user does not possess such a disk or does not know how to use one. In addition, an experienced programmer of a computer virus may hide the virus in DRAMs to infect the BIOS program each time the computer system is initiated, even after the user has purged the flash memory of the virus.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an intelligent computer initiation program recovery apparatus that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structures and methods particularly pointed out in the written description and claims thereof, as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided an intelligent computer initiation program recovery apparatus. The apparatus includes a first memory containing a first computer initiation program wherein the first memory permits the stored first initiation program to be altered, a read-only-memory containing a second computer initiation program, and a circuit coupled to the first memory and the read-only-memory wherein the circuit calculates a value from the first program and compares the calculated value against a predetermined value to enable the first memory when the calculated value equals the predetermined value and to enable the read-only-memory when the calculated value differs from the predetermined value.
In one aspect of the invention, the read-only-memory provides a warning when the calculated value differs from the predetermined value.
In another aspect of the invention, the circuit comprises a multiplexer coupled to the first memory and the read-only-memory for enabling one of the first memory and the read-only-memory.
In yet another aspect of the invention, the circuit comprises a logic circuit coupled to the multiplexer, wherein the logic circuit calculates the calculated value and compares the calculated value to the predetermined value, and wherein the logic circuit provides an output to the multiplexer.
In still another aspect of the invention, the apparatus further comprises a host coupled to the first memory, the read-only-memory and the circuit, wherein the host receives the first initiation program when the calculated value equals the predetermined value and receives the second initiation program when the calculated value differs from the predetermined value.
In yet another aspect of the invention, the circuit includes an AND gate to generate a reset signal wherein the AND gate has two inputs and receives a system reset signal on one of the two inputs.
Also in accordance with the invention, there is provided an intelligent computer initiation program recovery apparatus. The apparatus includes first means for storing a first computer initiation program and for permitting the stored first initiation program to be altered, second means for storing a second computer initiation program, and circuit means coupled to the first means and the second means for calculating a value from the first program and comparing the calculated value against a predetermined value to enable the first means when the calculated value equals the predetermined value and to enable the second means when the calculated value differs from the predetermined value.
In one aspect of the invention, the circuit means includes multiplexer means for enabling one of the first means and the second means, logic means coupled to the multiplexer means for calculating the calculated value and comparing the calculated value to the predetermined value, and gate means coupled to the logic means for generating a reset signal.
In another aspect of the invention, the apparatus further includes a host coupled to the gate means for receiving the reset signal, coupled to the first means for receiving the first initiation program when the calculated value equals the predetermined value, and coupled to the second means for receiving the second initiation program when the calculated value differs from the predetermined value.
Additionally in accordance with the invention, there is provided an intelligent computer initiation program recovery apparatus that includes a first memory for storing a first computer initiation program wherein the first memory permits the stored first initiation program to be altered, and a circuit coupled to the first memory wherein the circuit includes an embedded memory having stored therein a second initiation program, wherein the circuit calculates a value from the first program and compares the calculated value against a predetermined value, and wherein the circuit enables the first memory when the calculated value equals the predetermined value and enables the embedded memory when the calculated value differs from the predetermined value.
Also in accordance with the invention, there is provided a method for computer initiation program recovery. The method includes defining a predetermined reference value, calculating a value from a first computer initiation program stored in a first memory, comparing the calculated value to the predetermined reference value, enabling the first memory when the calculated value equals the predetermined reference value to provide access to the first computer initiation program stored therein, enabling a second memory containing a second computer initiation program when the calculated value differs from the predetermined reference value to provide access to the second computer initiation program stored therein, and providing a reset signal to a host system coupled to the first memory and the second memory wherein the host system receives one of the first computer initiation program and the second computer initiation program.
In one aspect of the invention, the predetermined reference value is the sum of the first initiation program address values.
In another aspect of the invention, the predetermined
Baderman Scott
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Winbond Electronics Corporation
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