Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-03-02
2003-04-08
Fabmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S329000, C257S330000, C257S332000, C438S259000, C438S270000, C438S271000, C438S289000
Reexamination Certificate
active
06545315
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to MOSFET transistors and more generally to DMOS transistors having a trench structure.
BACKGROUND OF THE INVENTION
DMOS (Double diffused MOS) transistors are a type of MOSFET (Metal On Semiconductor Field Effect Transistor) that use diffusion to form the transistor regions. DMOS transistors are typically employed as power transistors to provide high voltage circuits for power integrated circuit applications. DMOS transistors provide higher current per unit area when low forward voltage drops are required.
A typical discrete DMOS circuit includes two or more individual DMOS transistor cells which are fabricated in parallel. The individual DMOS transistor cells share a common drain contact (the substrate), while their sources are all shorted together with metal and their gates are shorted together by polysilicon. Thus, even though the discrete DMOS circuit is constructed from a matrix of smaller transistors, it behaves as if it were a single large transistor. For a discrete DMOS circuit it is desirable to maximize the conductivity per unit area when the transistor matrix is turned on by the gate.
One particular type of DMOS transistor is a so-called trench DMOS transistor in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin oxide layer and filled with polysilicon, allows less constricted current flow and thereby provides lower values of specific on-resistance. Examples of trench DMOS transistors are disclosed in U.S. Pat. Nos. 5,072,266, 5,541,425, and 5,866,931.
One problem with trench DMOS transistors is known as punch-through. Punch-through, which arises when the transistor channel is depleted, typically takes the form of a non-destructive leakage current prior to avalanche breakdown. It has been found that punch-through is particularly deleterious at higher transistor cell densities, notably at densities greater than about 18M/in2. Among the various causes of punch-through, one significant cause occurs during the formation of the trench gate. In particular, after the trench has been etched a sacrificial oxidation step is performed to smooth the trench sidewalls, which is then followed by deposition of the thin oxide layer. During the sacrificial oxidation and oxide deposition steps, dopant material leaches out of the adjacent channel (the so-called p-body) because dopant material (typically boron), segregates from the silicon into the gate oxide during the sacrificial oxidation step, which is performed at high temperatures. This problem is exacerbated at higher cell densities because the relative width of the channel decreases with respect to the surface area encompassed by the trench.
Punch-through is also aggravated when polysilicon is deposited to fill the trench because the dopant (typically phosphorous) employed in the polysilicon can penetrate through the gate into the p-body, which effectively reduces the concentration of carriers in the channel. This problem becomes more severe as the thickness of the gate oxide layer lining the trench is reduced.
U.S. Pat. No. 5,072,266 discloses a conventional sequence of processing steps that are employed to fabricate a trench DMOS transistor. In this process the p-body channel and the source regions are formed before the trench. As previously mentioned, however, during the formation of the trench dopant materials can leach out of the p-body, increasing punch-through. As a result, the depth of the trench and the pbody must be increased to compensate for the increase in punch-through. Moreover, the source regions may also be adversely effected during the formation of the trench because of silicon defects produced in the source regions during the oxidation steps used in forming the trench gate.
U.S. Pat. No. 5,468,982 attempts to reduce punch-through by forming the p-body after the trench gate has been etched and filled. This approach is not entirely satisfactory, however, since the formation of the p-body requires a diffusion step that involves high temperatures (typically 1100-1150° C.). The high temperatures allow the dopant material in the polysilicon that fills the trench to penetrate through the gate oxide at a greater rate, thus contributing to an increase in punch-through.
Accordingly, there remains a need for a process of fabricating a trench DMOS transistor that substantially reduces punch-through.
SUMMARY OF THE INVENTION
The present invention provides a method of forming a trench DMOS transistor. The method begins by providing a substrate of a first conductivity type. A body region, which has a second conductivity type, is formed on the substrate. A masking layer is formed which defines at least one trench. Next, the trench and an insulating layer that lines the trench are formed. A conductive electrode is then formed in the trench, which overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. The step of forming the trench includes the steps of etching the trench and smoothing the sidewalls of the trench with a sacrificial oxide layer before removal of the masking layer that defines the trench.
Because the present invention advantageously completes the steps of trench formation prior to removal of the patterned trench mask, dopant material is prevented from leaching leach out of the p-body since the patterned trench mask serves as a cap or barrier. Thus, punch-through is reduced.
In accordance with another aspect of the invention, the conductive electrode is formed from polysilicon. The step of forming the polysilicon conductive electrode may include the steps of depositing a layer of undoped polysilicon followed by a layer of doped polysilicon. These steps also reduces punch-through because the undoped polysilicon layer serves as a buffer layer to inhibit the penetration of dopant material through the insulating layer and into the body region.
REFERENCES:
patent: 5072266 (1991-12-01), Bulucea et al.
patent: 5468982 (1995-11-01), Hshieh et al.
patent: 6051488 (2000-04-01), Lee et al.
patent: 6312993 (2001-11-01), Hshich et al.
Hshieh Fwu-Iuan
So Koon Chong
Fabmy Wael
General Semiconductor Inc.
Louie Wai-Sing
Mayer Fortkort & Williams PC
Mayer, Esq. Stuart H.
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