Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-11-29

2003-07-15

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S298000, C257S300000, C257S326000, C257S384000, C257S412000

Reexamination Certificate

active

06593609

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as a DRAM, whose memory cell region includes a plurality of access transistors and memory capacitors connected to the drains of the access transistors and whose logic region includes a plurality of logic transistors. The present invention also relates to a method for fabricating the above semiconductor memory device.
2. Background Art
In a memory device having a memory cell region and a logic region, the logic transistors in the logic region have a silicide film formed on their sources and drains to lower the resistance of the source and the drain circuits. In addition, a silicide film is further formed on the gate electrodes of the logic transistor so that a “salicide” configuration is established to lower the resistance of the gate circuits. On the other hand, if a silicide film is formed on the sources and the drains of the access transistors in the memory cell region, the leakage currents of the sources and the drains increase, deteriorating the DRAM refresh performance. Therefore, it is not possible to apply a “salicide” configuration to the access transistors in the memory cell region. However, since it is strongly desired to reduce the resistance of the gate electrodes of the access transistors, it is preferred to apply a silicide technique only to the gate electrodes leaving the sources and the drains as they are.
To address such a need, for example, Japanese Patent Laid-Open No. 2000-269461 discloses a technique in which the distances between the access transistors in the memory region are reduced to bury the drains under an insulation film, and a silicide film is formed on the gate electrodes of the access transistors. However, since the sources of the access transistors to which bit lines are connected have a large area, they cannot be buried under the insulation film when the silicide film is formed. This means that the problem of the leakage currents flowing from the sources of the access transistors is left unsolved.
SUMMARY OF THE INVENTION
The present invention provides an improved semiconductor memory device in which a silicide film can be formed on the gate electrodes of the access transistors in a state that the sources and the drains of the access transistors have an insulation film of a sufficient thickness formed thereon regardless of their areas.
The present invention also provides an improved semiconductor memory device in which a silicide film can be formed on the gate electrodes of the access transistors in a state that the sources and the drains of the access transistors have an insulation film of a sufficient thickness formed thereon regardless of their areas, without making the fabrication process complicated.
According to one aspect of the present invention, a semiconductor device comprises a plurality of access transistors and memory capacitors connected to drains of the plurality of access transistors in a memory cell region a plurality of logic transistors in a logic region. The each logic transistor includes a first silicide film on a source and a drain, a gate electrode on a gate insulation film, a second silicide film on the gate electrode, a sidewall for the gate electrode, and an encircling insulation film encircling the sidewall. The each access transistor includes a gate electrode on a gate insulation film, a third silicide film on the gate electrode, and a laminated insulation film on a source and a drain of the each access transistor. The laminated insulation film is composed of a first film and a second film laminated on the first film and a top surface. The laminated insulation film is positioned at substantially the same height as that of the third silicide film. The first film is the same insulation film as that used as the sidewall of the each logic transistor and the second film is the same insulation film as that used as the encircling insulation film.
According to another aspect of the present invention, in the semiconductor memory device, the second silicide film and the third silicide film are made of a same material but the first silicide film is made of a different material.
According to another aspect of the present invention, the semiconductor memory device further comprises a bitline plug contact connected to the source (or the drain) of the each access transistor and a capacitor plug contact connected to the drain (or the source) of the each access transistor. The bit-line plug contact and the capacitor plug contact are formed through the laminated insulation film. The bit-line plug contact and the capacitor plug contact each have a fourth silicide film thereon, and a bit line and a memory capacitor are each connected to a respective fourth silicide film.
According to another aspect of the present invention, in the semiconductor memory device, the second silicide film, the third silicide film, and the fourth silicide film are made of a same material but the first silicide film is made of a different material.
According to another aspect of the present invention, in a method for fabricating a semiconductor memory device which includes a plurality of access transistors and memory capacitors connected to drains of the plurality of access transistors in a memory cell region, and a plurality of logic transistors in a logic region, a gate electrode is formed on a gate insulation film of each logic transistor and on a gate insulation film of each access transistor. An insulation film is coated on the gate electrode of the each logic transistor to form a sidewall for the gate electrode and on a source and a drain of each access transistor. A first silicide film is formed on a source and a drain of the each logic transistor. An insulation film is coated around the sidewall of the each logic transistor and is laminated on the source and the drain of the each access transistor so as to form a laminated insulation film. The logic region and the memory cell region are together polished so as to expose the gate electrode of the each logic transistor and the gate electrode of the each access transistor. The laminated insulation film on the source and the drain of the each access transistor are polished. A second silicide film and a third silicide film are formed on the gate electrode of the each logic transistor and on the gate electrode of the access transistor, respectively.
According to another aspect of the present invention, in the method for fabricating a semiconductor memory device, the second silicide film and the third silicide film are formed by using a material different from that of the first silicide film.
According to another aspect of the present invention, in the method for fabricating a semiconductor memory device, through the laminated insulation film, a bit-line plug contact connected to the source (or the drain) of the each access transistor is formed, and a capacitor plug contact connected to the drain (or the source) of the each access transistor is formed. When the logic region and the memory cell region are polished together, the bit-line plug contact and the capacitor plug contact are also polished. When the second silicide film and the third silicide film are each formed on a respective gate electrode, a fourth silicide film is formed on the bit-line plug contact and the capacitor plug contact.
Other and further objects, features and advantages of the invention will appear more fully from the following description.


REFERENCES:
patent: 5998252 (1999-12-01), Huang
patent: 6025620 (2000-02-01), Kimura et al.
patent: 6177306 (2001-01-01), Wu
patent: 6287911 (2001-09-01), Nobusawa
patent: 6417534 (2002-07-01), Nakahata et al.
patent: 2000-196017 (2000-07-01), None
patent: 2000-269461 (2000-09-01), None
Syd R. Wilson, Clarence J. Tracy, and John L. Freeman, Jr., “Handbook of Multilevel Metallization for Integrated Circuits,” Noyes Publ., Westwood, New Jersey, (1993), pp. 43-44.

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