Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-20
2003-04-22
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S313000
Reexamination Certificate
active
06552380
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-075080, filed Mar. 19, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
In accordance with high integration of semiconductor integrated circuits represented by DRAMs, the device area has been reduced from generation to generation. In a DRAM in which each memory cell comprises one transistor and one capacitor, reduction of the device area involves reduction of the area of capacitors for storing information, so the function of storing information is deteriorated.
Hence, in a DRAM, various countermeasures for maintaining a sufficient capacity for the capacitors have been taken so that the information storage function might not be deteriorated by reduction of the device area. Adoption of a capacitor having a three-dimensional structure is one of those countermeasures.
A trench capacitor is known as one of capacitors of this kind. It is important for the trench capacitor to bury a deep trench without causing a void or a seam.
FIGS. 6A
to
6
D are sectional views showing steps of a method for manufacturing a conventional trench capacitor which was proposed to achieve this object (Jpn. Pat. Appln. KOKAI Publication No. 10-56154.)
According to this conventional method, as shown in
FIG. 6A
, a mask pattern
82
is firstly formed on a silicon substrate
81
and the silicon substrate
81
is etched with the above mask pattern used as a mask by a RIE (Reactive Ion Etching) method, thereby to form a deep trench
83
in the silicon substrate
81
. A layered film consisting of a silicon oxide film, a silicon nitride film, and a silicon oxide film can be used for the mask pattern
82
.
Next, as shown in
FIG. 6B
, a collar insulating film
84
is formed, and thereafter, a capacitor insulating film
85
is deposited on the entire surface of the deep trench
83
. The collar insulating film
84
is formed as follows.
The inner surface of the trench
83
is oxidized thermally to form a thin oxide film (not shown). Next, a resist (not shown) is applied so as to fill the trench
83
after a silicon nitride film (not shown) having thickness of approximately 10 nm is deposited on the entire surface by a LPCVD method. The resist at an upper portion of the trench is exposed and developed. As a result, an inner wall of the upper portion of the trench is exposed. Next, the resist is peeled after the silicon nitride film and the silicon oxide film at the upper portion of the trench by a CDE method. Further, a side surface of the upper portion of the trench is selectively oxidized thermally with the silicon nitride film at a bottom portion of the trench used as a mask, thereby to form a collar oxide film
84
. Next, the silicon nitride film at a lower portion of the trench is peeled by using HF/glycerol. Finally, the silicon oxide film at the lower portion of the trench is removed.
Next, as shown in
FIG. 6C
, a thin polycrystalline silicon film
86
and an amorphous silicon film
87
containing impurities such as phosphorus or the like are deposited sequentially on the entire surface so as not to close the trench
83
. The thickness of the thin polycrystalline silicon film
86
is, for example, 20 nm. The thin polycrystalline silicon film
86
is used as a liner film and the amorphous silicon film
87
is used a node electrode.
Finally, as shown in
FIG. 6D
, the amorphous silicon film
87
is subjected to a heat treatment so that the amorphous silicon film
87
flows to fill the trench
83
.
This method is to fill the deep trench
83
with the amorphous silicon film
87
without causing any voids or seams, by utilizing the point that the amorphous silicon tends to move more easily than the polycrystalline silicon.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device and a method of manufacturing the same having a buried structure (in which a conductive film is buried in a deep trench) which can be realized easily.
To achieve the above object, a semiconductor device according to the present invention is comprises: a silicon substrate having a trench formed in a surface of the silicon substrate; a polycrystalline silicon film coating an inner surface of the trench such that the trench is not closed; and a conductive film made of material having a lower melting point than silicon and formed on the polycrystalline silicon film so as to fill the trench.
Further, a method of manufacturing a semiconductor device, according to the present invention, comprises steps of: forming a trench on a surface of a silicon substrate; coating an inner surface of the trench with a polycrystalline silicon film as a liner film such that the trench is not closed; forming a conductive film made of material having a lower melting point than silicon, on the polycrystalline silicon film, such that the trench is not closed; and flowing the conductive film so as to fill the trench, by performing a heat treatment on the conductive film.
The pressure during the heat treatment is preferably set higher than the pressure at which the conductive film is formed. Further, a heat treatment is preferably performed on the conductive film in a state that no oxide film exists on the surface of the conductive film.
In the present invention, when a trench is buried by a conductive film with a polycrystalline silicon film (liner film) inserted therebetween, the conductive film has a lower melting point than the polycrystalline silicon film. Therefore, in the step of flowing the conductive film by a heat treatment thereby to fill the trench (reflow step), the polycrystalline silicon film and the conductive film can be prevented from flowing integrally. Accordingly, a deep trench can be buried easily with a conductive film having an excellent buried form.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
REFERENCES:
patent: 5888876 (1999-03-01), Shiozawa et al.
patent: 6100132 (2000-08-01), Sato et al.
patent: 6180480 (2001-01-01), Economikos et al.
patent: 10-56154 (1998-02-01), None
Copy of U.S. Application No. 09/296,669, by Tsutomu Sato et al., entitled “Semiconductor Device and Method of Manufacturing the Same,” filed Apr. 22, 1999.
Copy of U.S. Application No. 09/650,748, by Tsutomu Sato et al., entitled “Semiconductor Substrate and its Fabrication Method,” filed Aug. 30, 2000.
Copy of U.S. Application No. 09/549,413, by Masaru Kito et al., entitled “Semiconductor Device and Manufacturing Method Thereof,” filed Apr. 14, 2000.
Mizushima Ichiro
Sato Tsutomu
Tsunashima Yoshitaka
Finnegan, Henderson Farabow, Garrett and Dunner L.L.P.
Kabushiki Kaisha Toshiba
Potter Roy
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