Row decoder of a NOR-type flash memory device

Details Row decoder of a NOR-type flash memory device Row decoder of a NOR-type flash memory device

2001-07-13

2003-04-01

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185090, C365S185110

Reexamination Certificate

active

06542406

ABSTRACT:

This application relies for priority upon Korean Patent Applications Nos. 2000-40212, filed on Jul. 13, 2000 and 2000-68999, filed on Nov. 20, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The invention generally relates to a semiconductor memory device and, more specifically, to a NOR-type flash memory device having a row decoder that occupies a smaller layout area over the memory device.
BACKGROUND OF THE INVENTION
Semiconductor memory devices are classified into volatile and nonvolatile types. The volatile semiconductor memory devices cannot retain data stored in their memory cells when a power is turned off, while the nonvolatile memory devices hold their data even during a power-off period. The nonvolatile memory devices are useful for applications that require stable data retention facilities or for portable systems.
As one of the nonvolatile memory devices, a NOR-type flash memory device employs EPROM (erasable and programmable read-only memory) cells, also referred to as flash EEPROM cells. The flash EEPROM cell is formed of a cell transistor as shown in FIG.
1
. The cell transistor is typically constructed of n-type source and drain regions
2
and
3
formed in a p-type semiconductor substrate
1
or a bulk region and spaced apart from each other as shown. The cell transistor also includes a floating gate
4
formed over a channel region between the source and drain regions and a control data
5
stacked over the floating gate
4
. The floating gate
4
is electrically isolated from the channel region through an oxide film, and an intermediate isolation film is interposed between the floating and control gates. The source region
2
is connected to a source line SL, and the drain region
3
is connected to a bitline BL. The control gate
5
is connected to a wordline WL.
FIG. 2
shows a construction of a conventional NOR flash memory device. A memory cell array is divided into a plurality of memory sectors
10
each of which includes a plurality of the EEPROM cells arranged in a matrix of rows controlled by wordlines WLX where x=0,1 . . . m columns (controlled by bitlines not shown in FIG.
2
.). A global wordline decoder
12
is arranged to select global wordlines GWL
0
~n extending over the memory sectors
10
, and a plurality of local decoder groups
14
are arranged to correspond with a plurality of the memory sectors
10
. Sector predecoders
16
are disposed to correspond with the local decoder groups
14
(and the memory sectors
10
).
The global wordlines are sourced or driven by the global wordline decoder
12
, with each of the global wordlines coupled to a plurality of local decoders in each row. The wordlines of each memory sector
10
, WL
0
~WLm, are subdivided into plural segments each of which in turn has plural wordlines (e.g., eight wordlines). Each of the local decoders is assigned to one of the segments of wordlines for each memory sector
10
. Therefore, the wordlines of a segment, e.g., WL
0
~WL
7
, are connected in common to their corresponding local decoder LD
1
~LDn. Each sector predecoder
16
applies selection signals S
1
(i=0~8) to the local decoders LD
0
~LDn to charge a corresponding one of the memory sectors
10
.
A typical local decoder (e.g. LD
0
), as shown in
FIG. 3
, is constructed of units LDU
0
~LDU
7
each of which corresponds to one of the segmented wordlines WL
0
~WL
7
. A given unit, e.g. LDU
0
, is formed of a transmission gate TG
0
and a NMOS transistor MN
0
responsive to one of the global wordlines, e.g. GWL
0
. The transmission gates TG
0
~TG
7
transfer the selection signals S
0
~S
7
to the wordlines WL
0
~WL
7
in response to a signal (i.e. a global wordline decoding signal) on the global wordline GWL
0
, and the NMOS transistors MN
0
~MN
7
transfer an erasure voltage Vex to the wordlines WL
0
~WL
7
in response to the global decoding signal supplied through the global wordline GWL
0
.
In programming and erasing the NOR flash device, bias voltages are supplied to the global wordlines, the segmented wordlines, and the selection signals as illustrated in TABLE 1 below.
TABLE 1
GWL
Selected Sector
Operation
Unsel.
Sel.
Unsel.
Sel.
Unsel.
Unselected Sector
mode
Sel. WL
WL
Si
S
1
WL
WL
Vex
Si
WL
Vex
Program
  9 V
0 V
  9 V
0 V
  9 V
0 V
 0 V
0 V
0 V
0 V
Read-out
4.5 V
0 V
4.5 V
0 V
4.5 V
0 V
 0 V
0 V
0 V
0 V
Erasure
−9 V
0 V
−9 V
−9 V
0 V
0 V
0 V
The programming operation is performed by selecting one of the global wordlines and one of the selection signals from the sector predecoders
16
. The selected global wordline, e.g., GWL
0
, is charged up to 9V while the unselected global wordlines GWL
1
~GWLn are set to 0V. The selected selection signal, e.g. S
0
, is charged to 9V while the unselected selection signals S
1
~S
7
are held to 0V. The erase voltage Vex is maintained at 0V during programming.
Regarding the selected global wordline GWL
0
with the bias conditions shown in TABLE 1, the transmission gates TG
0
~TG
7
are turned on while the NMOS transistors MN
0
~MN
7
are turned off. Then, the activated selection signal S
0
of 9V is driven into the wordline WL
0
through the transmission gate TG
0
, while the other wordlines WL
1
~WL
7
(deselected) are connected to the selection signals S
1
~S
7
of 0V through the transmission gates TG
1
~TG
7
. As for the unselected global wordlines GWL
1
~GWLn, their corresponding wordlines are connected to the erase voltage Vex of 0V (inactive) through the NMOS transistors MN
0
~MN
7
while the transmission gates TG
0
~TG
7
are being turned off.
The read-out operation is performed at 4.5V, instead of 9V in the programming operation. The 4.5V read-out voltage is established on the selected global wordline GWL
0
and on selection signal S
0
.
The erase operation is carried out sector by sector. Memory cells in a sector are erased in a unit cycle of the erasure operation. As shown in TABLE 1, the global wordlines GWL
0
~GWLn are charged to −9V and the selection signals S
0
~S
7
are set to 0V. The erase −9V Vex voltage is applied to the local decoders. The transmission gates TG
0
~TG
7
are turned off while the NMOS transistors MN
0
~MN
7
are turned on to drive Vex of −9V onto the wordlines WL
0
~WL
7
. Then, the wordlines of a selected sector are charged to the −9V bias voltage.
However, the local decoder shown in
FIG. 3
needs three MOS transistors, including two for the transmission gate, to operate one wordline for programming, reading-out, and erasing. As a result, the circuit area occupied by the local row decoders undesirable increases the layout dimension and chip size.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a nonvolatile semiconductor memory device having row decoders that occupy a smaller area therein.
In order to achieve the object of the invention, a nonvolatile semiconductor memory device includes a plurality of first wordlines, a plurality of second wordlines coupled to memory cells, the second wordlines being assigned to each of memory sectors, a plurality of transistors each of which connects the first wordline to the second wordline, and a circuit for controlling the transistors in common. One of the first wordlines is connected to one of the second wordlines through one of the transistors.
The transistor is a depletion type having a negative threshold voltage. The device also has a redundant memory sector formed of a plurality of redundant memory cells which are coupled to redundant wordlines, the redundant wordlines being each connected to the first wordlines through corresponding transistors, and a circuit for controlling the transistors in common.
A decoding circuit for selecting the first wordlines includes a loop (by which is meant the fuse
126
that is arranged parallel with a VERn-gated transistor
127
in
FIG. 5
) to isolate the first wordline from a voltage source when the first wordline is involved in a defective cell. The decoding circuit inc

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