Mixed mode multi-level indicator

Details Mixed mode multi-level indicator Mixed mode multi-level indicator

2001-07-13

2003-03-18

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185110, C365S185120, C365S168000

Reexamination Certificate

active

06535419

ABSTRACT:

BACKGROUND
A flash memory cell can be a field effect transistor (FET) that includes a select gate, a floating gate, a drain, and a source. A cell can be read by grounding the source, and applying a voltage to a bitline connected with the drain. By applying a voltage to the wordline connected to the select gate, the cell can be switched on and off.
Programming a cell includes trapping excess electrons in the floating gate to increase voltage. This reduces the current conducted by the memory cell when the select voltage is applied to the select gate. The cell is programmed when the cell current is less than a reference current when the select voltage is applied. The cell is erased when the cell current is greater than the reference current and the select voltage is applied.
Memory cells with only two programmable states contain only a single bit of information, such as a “0” or a “1”. A multi-level cell (“MLC”) is a cell that can be programmed with more than one voltage level. Each voltage level is mapped to corresponding bits of information. For example, a single multi-level cell can be programmed with one of four voltage levels, e.g. −2.5V, 0.0V, +1.0V, +2.0V that correspond to binary bits “00”, “01”, “10”, and “11”, respectively. A cell that is programmable at more voltage levels can store more bits of data based on Eqn. 1.
N
=2
{circumflex over ( )}B
  Eqn. 1
B is the number of bits of data stored
N is the number of voltage levels.
Thus, a 1 bit cell requires 2 voltage levels, a 2 bit cell requires 4 voltage levels, a 3 bit cell requires 8 voltage levels, and a 4 bit cell requires 16 voltage levels.
FIG. 1
shows a representation of a single bit programming voltage level diagram
100
. The “erase state” program distribution
102
(“erase state”), and the “programmed state” program distribution
104
(“programmed state”)represent a single bit being either a “0” or a “1”, respectively. The voltage between the upper end
106
of the erase state
102
and ground
108
(0.0V) is the “erase margin.” The voltage between ground
108
(0.0V) and the lower end
110
of the programmed state
102
and is the “program margin.” The erase state program distribution
102
is center near −2.5V and the programmed state program distribution
104
is centered around 2.25V. The read point can be at ground
108
or anywhere between lines
106
and
110
, preferably near the mid-point between lines
106
and
110
.
FIG. 2
shows a representation of a four level multilevel cell program voltage diagram
200
. The program distribution (“distribution”) of the four levels are shown at
210
,
212
,
214
, and
216
respectively. For example, the programming distributions are located at approximately −2.5V, 0.0V, 0.8V, and 2.0V and the width of the programming distributions are approximately 100 to 600 mV. A four level multilevel memory cell can be programmed with any one of these voltage levels. Because the cell can store one of four binary values it can store 2 bits of information. The program margin (also called “margin”, “data margin”, or “guard band”) is the voltage levels between distributions that is not normally used. For example, the program margins between program distributions
212
,
214
, and
216
are approximately 800 mV to 100 mV wide. The program margin between program distributions
210
and
212
is approximately 2.0V.
BRIEF SUMMARY OF PREFERRED EMBODIMENTS
A memory device having a plurality of memory cells that are group into at least two group of cells. Each cell is capable of being programmed in at least two modes. A mode indicator is associated with each group of cells. The mode indicator indicates which programming mode is used to access the cells. The mode indicator is one or more bits and optionally is user selectable.


REFERENCES:
patent: 5574879 (1996-11-01), Wells et al.
patent: 5844841 (1998-12-01), Takeuchi et al.
patent: 5859795 (1999-01-01), Rolandi
patent: 5930167 (1999-07-01), Lee et al.
patent: 6104641 (2000-08-01), Itou
patent: 6297988 (2001-10-01), Parker et al.
patent: 6353553 (2002-03-01), Tamada et al.
patent: 19904542 (2000-01-01), None
patent: 0763828 (1997-03-01), None

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