Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2001-09-17
2003-05-20
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S233100
Reexamination Certificate
active
06567321
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and, more particularly, to a synchronous DRAM including a dedicated strobe signal used only for commands and addresses and an associated method.
2. Description of the Related Art
To improve system performance, the integration and speed of semiconductor memory devices, in particular, DRAMs is continuously increasing. Notwithstanding these continuous advancements, a DRAM capable of processing more data at higher speed is necessary. Accordingly, a synchronous DRAM that operates synchronous with a system clock has been developed for high speed operation. The transmission speed of data has significantly increased with the appearance of the synchronous DRAM.
In the conventional synchronous DRAM, the input and output of data are synchronous with a system clock. Commands and addresses are input responsive to a system clock. Accordingly, the commands and addresses must be transmitted from a memory controller to the synchronous DRAM within a predetermined cycle time of the system clock. Even though the commands and addresses arrive at the synchronous DRAM before the system clock, the commands and addresses are provided internally responsive to the arrival of the system clock. Therefore, the latency corresponding to the time difference between the arrival of the commands and addresses and the arrival of the system clock increases in the conventional synchronous DRAM. Also, when the cycle time of the system clock is reduced because of increased system clock frequency, it is difficult to transmit commands and addresses to all synchronous DRAMs in a memory module within a single clock cycle time in a memory module having multiple synchronous DRAMs.
SUMMARY OF THE INVENTION
It is an object of the invention to overcome the disadvantages associated with conventional synchronous DRAMS.
It is another object of the present invention to provide a synchronous DRAM that is capable of reducing a latency associated with a time difference between the arrival of commands and addresses and the arrival of a system clock and safely transmitting the commands and addresses to all the synchronous DRAMs of a memory module within a clock cycle time even when the frequency of the system clock increases.
It is yet another object of the present invention to provide a method of inputting commands and addresses that is capable of reducing the latency corresponding to a time difference between the arrival of commands and addresses and the arrival of a system clock and safely transmitting the commands and addresses to all the synchronous DRAMs of a memory module within a clock cycle time even when the frequency of the system clock increases.
A semiconductor memory device operating responsive to a system clock is provided. The device includes a strobe signal input buffer circuit for receiving a dedicated command and address strobe signal. A command input buffer circuit receives commands responsive to an output signal of the strobe signal input buffer circuit and latches the received commands. An address input buffer circuit receives addresses responsive to the output signal of the strobe signal input buffer circuit and latches the received addresses. The dedicated command and address strobe signal is different from the system clock.
In one embodiment, the dedicated command and address strobe signal is activated only when the commands and the addresses are input to the semiconductor memory device. In another embodiment the dedicated command and address strobe signal is a free running clock that continuously toggles.
A method of inputting commands and addresses responsive to a system clock is provided. The method includes receiving a dedicated command and address strobe signal, receiving commands responsive to the reference edge of the dedicated command and address strobe signal, and latching the received commands. The method further includes receiving addresses responsive to the reference edge of the dedicated command and address strobe signal and latching the received addresses, wherein the dedicated command and address strobe signal is different from the system clock.
In one embodiment, the dedicated command and address strobe signal is activated only when the commands and the addresses are input to the semiconductor memory device. In another embodiment, the dedicated command and address strobe signal is a free running clock that continuously toggles.
REFERENCES:
patent: 5805901 (1998-09-01), Dornier et al.
patent: 6064625 (2000-05-01), Tomita
patent: 6091663 (2000-07-01), Kim et al.
patent: 6285625 (2001-09-01), Vogley
Ho Tu-Tu
Nelms David
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