Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
2000-02-22
2003-04-22
Butler, Dennis M. (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C713S400000, C714S025000
Reexamination Certificate
active
06553506
ABSTRACT:
TECHNICAL FIELD
This invention relates to an information processing device and electronic equipment.
BACKGROUND OF ART
There has recently been increasing demand for the incorporation of microcomputers that are capable of implementing high-level information processing into electronic equipment such as game machines, car navigation systems, printers, and portable information terminals. The thus-incorporated microcomputer is usually mounted on a user board that is called a target system. A software development support tool called an in-circuit emulator (ICE) is widely used for supporting the development of software to be used in the target system.
With an ICE, it is necessary to transfer data for debugging, between the microcomputer installed in the target system and the external debugging tool. In such a case, a method called the synchronous method or another called start-stop synchronization is used as the transfer method. It is also desirable with an ICE that there are as few communication lines between the microcomputer and the debugging tool as possible. In addition, it is desirable that there should be as few sampling errors in the transferred data as possible.
However, if transfer is by the synchronous method, it is necessary to provide four communication lines between a microcomputer
340
(an information processing device) and a debugging tool
342
(a second information processing device), as shown in FIG.
1
A. In other words, it is necessary to have a TXD line (for send data), a TCLK line (for a TXD sampling clock signal), an RXD line (for receive data), and an RCLK line (for an RXD sampling clock signal). Thus the number of communication lines increases unnecessarily.
If transfer is by start-stop synchronization, on the other hand, the microcomputer
340
and the debugging tool
342
each have a clock signal of substantially the same frequency, as shown in FIG.
1
B. Assume, by way of example, that the microcomputer
340
has a clock signal CLK
1
and the debugging tool
342
has a clock signal CLK
2
, where CLK
1
and CLK
2
have substantially the same frequency. The microcomputer
340
generates a sampling clock signal SMC
1
by dividing the frequency of CLK
1
, and uses this SMC
1
to sample each bit of data (start bit, data bits D
0
to D
7
, and stop bit) that is transferred by start-stop synchronization, as shown in FIG.
2
A. Similarly, the debugging tool
342
generates a sampling clock signal SMC
2
by dividing the frequency of CLK
2
, and uses this SMC
2
to sample each bit of data (start bit, data bits D
0
to D
7
, and stop bit) that is transferred by start-stop synchronization, as shown in FIG.
2
B.
However, with this start-stop synchronization, if the operating frequency of the CPU comprised within the microcomputer
340
increases and thus the frequencies of CLK
1
and CLK
2
increase, the frequencies of SMC
1
and SMC
2
also increase and thus it is more likely that sampling errors will occur in the transferred data. Conversely, it is not possible to increase the frequencies of SMC
1
and SMC
2
to any level at which sampling errors occur in the transferred data. This means that it is not possible to debug the microcomputer
340
in an environment in which it operates at a high speed. In other words, the clock frequency of microcomputer must be reduced during debugging.
DISCLOSURE OF THE INVENTION
This invention was devised in the light of the above described technical problems, and has as an objective thereof the provision of an information processing device and electronic equipment that are capable to transferring data rapidly by start-stop synchronization.
In order to solve the above technical problems, this invention relates to an information processing device comprising a first communication means for transferring data by start-stop synchronization to and from a second communication means comprised within a second external information processing device, wherein the first communication means comprises: a first frequency division circuit for dividing the frequency of a first clock signal to generate a first sampling clock signal for sampling each bit of data transferred by start-stop synchronization; and a circuit for performing at least one of data reception and transmission, based on the first sampling clock signal; and wherein the first communication means supplies the first clock signal to the second information processing device as a signal that enables a second frequency division circuit comprised within the second communication means to generate a second sampling clock signal.
In this aspect of the invention, a first clock signal is used in common by the information processing device and the second information processing device. The first and second sampling clock signals are generated by dividing the frequency of this common first clock signal. The information processing device uses the first sampling clock signal to sample the bits of data that is transferred by start-stop synchronization, and the second information processing device uses the second sampling clock signal to sample the bits of data that is transferred by start-stop synchronization. It is therefore possible to prevent any slippage between the frequencies of these first and second sampling clock signals, which makes it possible to prevent the occurrence of sampling errors in the transferred data, in an efficient manner. As a result, it is possible to transfer data at the most suitable fast communication speed.
The first communication means may comprise a first division ratio control means for controlling the division ratio in the first frequency division circuit; and a second division ratio control means comprised within the second communication means changes the division ratio in accordance with the frequency of the first clock signal, and wherein when division ratio data which indicates the changed division ratio has been transferred to the first communication means, the first division ratio control means may change the division ratio in the first frequency division circuit based on the transferred division ratio data. This configuration ensures that, if the frequency of the first clock signal falls, the division ratio can be made small accordingly. This makes it possible to prevent the frequencies of the first and second sampling clock signals from falling too far, and also prevent the communication speed from falling. As a result, data can always be transferred at the most suitable fast communication speed, regardless of the magnitude of the frequency of the first clock signal.
The information processing device of this invention may further comprise a central processing unit for executing instructions; wherein the first communication means transfers data for debugging to and from the second information processing device that acts as a debugging tool. This configuration makes it possible to keep the speed with which data is transferred between the microcomputer (information processing device) and the debugging tool (second information processing device) at the optimal high speed. In particular, the clock frequency of the microcomputer often varies with each user who is using this microcomputer. The transfer speed for data therefore also changes with such changes in the clock frequency of the microcomputer. However, this aspect of the invention ensures that the first and second division ratios also change if the user of the microcomputer changes the clock frequency of the microcomputer. As a result, transfer can be done at the optimal communication speed in accordance with clock signals of various frequencies that the user can use, without lowering the communication speed in the end.
In the information processing device of this invention, the first clock signal may be used as a clock signal for sampling trace data after a transition from a debugging mode to a user program execution mode. This configuration makes it unnecessary to provide a new clock signal terminal for sampling trace data. It is therefore possible to design the information processing device to have a lowe
Hijikata Yoichi
Kudo Makoto
Butler Dennis M.
Oliff & Berridg,e PLC
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