Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
2001-10-05
2003-03-11
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S160000, C711S166000, C710S010000, C710S074000, C710S104000, C713S001000
Reexamination Certificate
active
06532526
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present disclosure pertains to the field of data processing systems. More particularly, the present disclosure pertains to initializing or configuring a memory devices in a memory channel.
2. Description of Related Art
Memory devices and memory subsystems typically have certain initialization steps and/or register values that need to be programmed prior to normal operation. Recommended steps and values are often detailed in a memory specification provided to system designers who design other system hardware interfacing with the memory devices. Unfortunately, memory specifications may change, and new initialization sequences and/or register values may be desirable.
To implement a new system compliant with a revised specification, expensive hardware changes may be required. Additionally, if more optimal initialization values or sequences are later discovered, they may not be implemented due to the high overhead of making hardware changes. Present systems do not provide a flexible memory initialization technique that may advantageously allow initialization sequences to be altered or optimized after hardware components have been completed.
One channel (i.e., a bus configuration) which requires a significant amount of initialization prior to proper operation is a Rambus™ Direct Rambus Dynamic Random Access Memory Channel (a Direct RDRAM™ Channel). This channel is described in detail in documentation available from Rambus Corporation of Mountain View, Calif. RDRAM memories and memory controllers interfacing with a Rambus channel have various registers that need to be programmed during the initialization process.
One method of initializing a direct RDRAM channel is described in the RMC.d1 Data Sheet, which describes a Direct Rambus™ Memory Controller (RMC). The RMC, however, utilizes an “Init Block” as a part of an application specific integrated circuit (ASIC) to implement initialization procedures (see
FIG. 7
, p. 16 and p. 72, et seq.). The Init Block is simply activated using two init signals and thereafter performs a routine hard-wired into the Init Block ASIC hardware.
Thus, the prior art in general may not provide an adequate method and apparatus for configuring a set of memory devices. A hard-wired solution such as the RMC ASIC inherently lacks the flexibility to allow rapid alteration of initialization sequences in order to optimize initialization or to contend with a changing memory specification. A flexible memory initialization technique could advantageously be utilized in a Direct Rambus™ bus or in any other memory system requiring significant initialization or configuration.
SUMMARY
A method and apparatus for configuring memory devices is disclosed. A disclosed bus controller includes a storage location and a control circuit. The control circuit is coupled to perform an initialization operation when a value indicating that initialization operation is stored in the storage location. The initialization operation is selected from one of a set of initialization operations that the control circuit is capable of performing.
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Nizar Puthiya K.
Stevens William A.
Intel Corporation
Lam Peter
Namazi Mehdi
Yoo Do Hyun
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