Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material
Reexamination Certificate
1999-04-02
2003-01-07
Padgett, Marianne (Department: 1762)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
C427S535000, C427S536000, C427S539000, C438S702000, C438S763000, C438S780000, C438S787000, C438S782000, C438S790000, C438S788000
Reexamination Certificate
active
06503818
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to the field of low dielectric constant dielectric layers. More particularly, the invention relates to the utilization of low dielectric constant dielectric layers within composite dielectric layers employed in microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by, microelectronics dielectric layers.
As microelectronics integration levels have increased and patterned microelectronics conductor layer linewidth dimensions have decreased, it has become more common within the art of microelectronics fabrication to employ low dielectric constant dielectric layers formed interposed between the patterns of patterned microelectronics conductor layers within microelectronics fabrications. Low dielectric constant dielectric layers are desirable interposed between the patterns of patterned microelectronics conductor layers within microelectronics fabrications since such low dielectric constant dielectric layers typically provide microelectronics fabrications with enhanced microelectronics fabrication speed, reduced microelectronics fabrication parasitic capacitance and attenuated patterned microelectronics conductor layer cross-talk
Of the methods and materials which may be employed for forming low dielectric constant dielectric layers interposed between the patterns of patterned microelectronics conductor layers within microelectronics fabrications, methods which employ low dielectric constant dielectric materials such as but not limited to organic polymer spin-on-polymer (SOP) dielectric materials (including but not limited to polyimide organic polymer spin-on-polymer (SOP) dielectric materials, poly (arylene ether) organic polymer spin-on-polymer (SOP) dielectric materials and fluorinated poly (arylene ether) organic polymer spin-on-polymer (SOP) dielectric materials), amorphous carbon dielectric materials (including fluorinated amorphous carbon dielectric materials) and silsesquioxane spin-on-glass (SOG) dielectric materials (including but not limited to hydrogen silsesquioxane (HSQ), carbon bonded methylsilsesquioxane (MSQ) and carbon bonded fluorocarbon silsesquioxane (FSQ) dielectric materials) are particularly desirable within the art of microelectronics fabrication. Such methods and materials are desirable due in particular to the ease of fabrication of dielectric layers by spin-on methods or by chemical vapor deposition (CVD) methods and the resulting low dielectric constant of the low dielectric constant dielectric layers, which typically exhibit homogeneous dielectric constant values ranging from about 2.5 to about 3.3. For comparison purposes, conventional silicon containing dielectric layers formed of silicon containing dielectric materials such as but not limited to silicon oxide dielectric materials and silicon nitride dielectric materials employed within microelectronics fabrications typically exhibit homogeneous dielectric constants within a range of from about 4.0 to about 4.4.
Within microelectronics fabrications, low dielectric constant dielectric layers typically have formed thereupon a cap layer of silicon containing dielectric material such as, for example, silicon nitride. One purpose of the cap layer is to furnish a hard mask layer for pattern transfer of a photolithographically defined pattern in the cap layer to the underlying low dielectric constant dielectric layer by methods as are known in the art of microelectronics fabrication, such as oxygen plasma etching in the case of organic polymer low dielectric constant dielectric layers. Another purpose of the cap layer is to serve as a moisture barrier layer when the underlying low dielectric constant dielectric layer is formed from a spin-on-glass (SOG) low dielectric constant material or other moisture sensitive material.
While low dielectric constant dielectric layers have found increasing applications within microelectronics fabrications, their employment in microelectronics fabrications is not without problems. In particular, there is often observed delamination of the silicon-containing dielectric cap layer from the low dielectric constant dielectric layer. In addition, there is frequently a need for a barrier layer impervious to moisture to protect the low dielectric constant dielectric layer from degradation.
It is therefore towards the goal of forming within microelectronics fabrications low dielectric constant dielectric layers with enhanced adhesion to overlying silicon containing dielectric layers such as silicon nitride cap dielectric layers that the present invention is more generally directed.
Various methods have been disclosed within the art of microelectronics fabrications for forming composite dielectric layers with desirable properties within microelectronics fabrications. The provision of adequate adhesion between the component layers of a composite dielectric layer structure is a primary object of the art, as is the capability of filling gaps and other non-planar features of the underlying substrates employed in microelectronics fabrications. These objects are achieved by methods which are conventional in the art such as spin-on methods, chemical vapor deposition (CVD) methods and plasma assisted chemical vapor deposition (PECVD) methods.
For example, Chen, in U.S. Pat. No. 5,635,425, discloses a method for improving adhesion of a patterned overlying dielectric layer formed by chemical vapor deposition (CVD) from TEOS vapor to an underlying dielectric layer and/or conductor layer within a microelectronics fabrication. The method employs simultaneous or sequential exposure of the underlying dielectric or conductor layers to a nitrogen plasma incidental to forming the overlying dielectric layer.
Further, Wang, in U.S. Pat. No. 5,554,567, discloses a method for improving adhesion of an overlying dielectric layer to the surface of an underlying dielectric layer where the underlying dielectric layer is formed of a spin-on-glass (SOG) dielectric material. The method employs a vacuum heat treatment of the spin-on-glass (SOG) dielectric material prior to formation of the overlying layer, which is deposited upon the underlying dielectric layer without breaking vacuum.
Still further, Jang et al., in U.S. Pat. No. 5,536,681, disclose a method for improving gap filling characteristics of silicon oxide layers deposited over patterned substrate layers employing an ozone assisted chemical vapor deposition (CVD) method employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material. The method employs a selective nitrogen plasma treatment of upper lying portions of a silicon oxide liner layer formed upon the patterned substrate layer to provide a retarded growth rate of the gap filling silicon oxide dielectric layer upon the upper lying portions of the silicon oxide liner layer in comparison with the lower lying portion of the silicon oxide liner layer.
Finally, Jain et al., in U.S. Pat. No. 5,403,780, disclose a method for forming a silicon oxide dielectric layer with enhanced planarization, etchback margin and reliability within a semiconductor integrated circuit microelectronics fabrication. The method employs a silicon rich silicon oxide underlayer of refractive index greater than 1.50. Thereupon is formed a second layer of silicon oxide deposited By chemical vapor deposition (CVD) employing tetra-ethyl-ortho-silicate (TEOS) as the silicon source material.
Desirable in the art of microelectronics fabrication are additional methods and materials for forming with enhanced adhesion composite dielectric layers employing low dielectric constant dielectric materials.
It is towards the foregoing goal that the present invention is generally and specifically directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide within a microelectronics fabrication a method for morning with enhanced interfacial adhesion a compo
Ackerman Stephen B.
Padgett Marianne
Saile George O.
Stanton Stephen G.
Taiwan Semiconductor Manufacturing Company
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