Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2000-08-15
2003-05-20
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S156000
Reexamination Certificate
active
06567902
ABSTRACT:
BACKGROUND OF THE INVENTION
A. Field of the Invention
The present invention relates generally to communication systems and, more particularly, to systems and methods for packing data from a source register into a destination register.
B. Description of Related Art
Some conventional systems include source and destination registers. During operation, data from a source register that may contain some invalid data bytes may be transferred to a destination register that stores valid data bytes in contiguous locations. The resulting problem of transferring the valid bytes of data from the source register to contiguous locations in the destination register may be referred to as “packing.” The problem becomes particularly troublesome when the invalid data bytes are randomly located amidst valid data bytes in the source register.
As a result, a need exists for a mechanism that packs non-contiguous valid bytes of data from a source register to contiguous locations in a destination register.
SUMMARY OF THE INVENTION
Systems and methods consistent with the present invention address this need by providing a packing mechanism that permits valid bytes of data from non-contiguous locations in a source register to be transferred to contiguous locations in a destination register.
In accordance with the purpose of the invention as embodied and broadly described herein, a data packing system includes a source memory, a destination memory, and a data packer. The source memory stores data in source storage locations. The data includes valid data and invalid data. The destination memory stores at least some of the data from the source memory in destination storage locations. The destination memory stores the valid data in contiguous ones of the destination storage locations. The data packer transmits the valid data from the source storage locations to the contiguous destination storage locations.
In another implementation consistent with the present invention, a method packs data from source storage locations of a source memory to destination storage locations of a destination memory. The data includes valid data and invalid data. The method includes storing the data in the source storage locations, at least some of the invalid data being interspersed among the valid data in the source storage locations; generating addresses for each of the valid data; transferring the valid data from the source storage locations to contiguous ones of the destination storage locations using the generated addresses and the invalid data to other ones of the destination storage locations; and storing the valid data and invalid data in the destination storage locations of the destination memory.
In yet another implementation consistent with the present invention, a data packer packs data from source storage locations in a source register into destination storage locations in a destination register. The data includes valid and invalid data. The data packer includes at least one comparator and at least one multiplexer. The comparator generates at least one selection signal. The multiplexer receives the valid and invalid data from the source storage locations as inputs and transmits the valid data to contiguous ones of the destination storage locations from ones of the source storage locations in response to the selection signal.
In a further implementation consistent with the present invention, a method packs data from source storage locations in a source register into destination storage locations in a destination register. The data includes valid and invalid data. The method includes generating a plurality of selection signals; transferring the valid data from ones of the source storage locations to contiguous ones of the destination storage locations in response to the selection signals; and sending the invalid data from other ones of the source storage locations to other ones of the destination storage locations in response to the selection signals.
In another implementation consistent with the present invention, a computer-readable memory device contains a data structure, including data byte areas, valid byte indicator areas, and valid byte address areas. The data byte areas store a valid data byte or an invalid data byte. The valid byte indicator areas store indications of whether a corresponding one of the data byte areas stores a valid data byte or an invalid data byte. The valid byte address areas store addresses when a corresponding one of the data byte areas stores a valid data byte.
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Chen Dev
Padmanabhan Ramesh
Bataille Pierre-Michel
Harrity & Snyder L.L.P.
Juniper Networks. Inc.
Kim Matthew
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