Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
Reexamination Certificate
2000-11-29
2003-09-16
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Data formatting to improve error detection correction...
C714S052000, C714S753000, C714S765000, C714S785000
Reexamination Certificate
active
06622268
ABSTRACT:
BACKGROUND
1. Field
This invention relates to data error reporting, and more specifically to propagating error status over an error checking and correcting (ECC) channel.
2. Background
Frequently, data that is read out of electronic devices, such as storage devices, input/output devices, etc., have parity bits or other types of check bits associated with the data. The check bits notify a receiver of the data whether the data being received is good data or whether the data has errors. If the data read from a memory or other source is to be received by one device and then sent to another device, the second receiving device needs to be aware that the data read (e.g., from a memory), is bad and has errors. However, if the error checking and correcting (ECC) that was used for the data in memory is different from the ECC used on the channel to send the data to the second receiving device, a different ECC code may need to be generated for the data that is read out of memory before sending the data to the second receiving device across the channel. Therefore, if data read from a memory or other device is corrupted (i.e., the data from memory has an uncorrectable error), the device receiving the data may compute new check bits with different ECC that is used on the channel, and send the data and new check bits to the second receiving device. At the second receiving device, everything looks fine regarding the validity of the data (since new check bits were generated), but this device may have actually received corrupted data. Therefore, the second receiving device needs to be notified that the data being received is corrupted and has an uncorrectable error.
One way to notify the second receiving device that the data being received has an uncorrectable error is to add an additional signal line to the second receiving device notifying this device when the data being received has an uncorrectable error. However, this requires the addition of another wire and possibly other hardware to the second receiving device. A second option is to purposely corrupt the data being sent to second receiving device again so that when the second receiving device receives the data it will detect an error. Since many channels and devices use single error correction (SEC) and double error detection (DED), injecting two errors into the data by the first receiving device before sending the data to the second receiving device will alert the second receiving device that the data has one or more uncorrectable errors. One way to inject two errors into the data is to flip two check bits before sending the data and check bits over the channel.
However, it is possible to get an additional error in the channel. If there is an error in the channel, this additional error may mask the injected errors, therefore, hiding the fact that the data contains an uncorrectable error. Therefore, a single bit error that occurs on the channel may alias the data to no error or to a single bit error, therefore, masking the uncorrectable error from the second receiving device. Since the first receiving device may be streaming data through the channel to the second receiving device, it is desired to insure that knowledge of uncorrectable errors get to the second receiving device.
Moreover, if the ECC code used at the second receiving device can only detect single and double bit errors, if four errors occur in the data sent across the channel, this may mask the fact that any error exists at all and the data may appear to have no errors to the second receiving device.
Therefore, a need exists for a more robust mechanism for propagating error status information over an ECC protected channel that is robust in the presence of single bit errors that may occur on the ECC protected channel.
REFERENCES:
patent: 5291496 (1994-03-01), Andaleon et al.
patent: 5856987 (1999-01-01), Holman
patent: 6101614 (2000-08-01), Gonzales et al.
patent: 6490703 (2002-12-01), de la Iglesia et al.
patent: 60064529 (1985-04-01), None
Dildine R. Stephen
Huter Jeffrey B.
Intel Corporation
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