Method of forming a field effect transistor

Details Method of forming a field effect transistor Method of forming a field effect transistor

2000-11-15

2003-07-29

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S164000, C438S296000

Reexamination Certificate

active

06599789

ABSTRACT:

TECHNICAL FIELD
This invention relates to methods of forming field effect transistors, to methods of forming integrated circuitry, and to integrated circuitry.
BACKGROUND OF THE INVENTION
Semiconductor processors continue to strive to reduce the size of individual electronic components, thereby enabling smaller and denser integrated circuitry. One typical circuitry device is a field effect transistor. Such typically includes opposing semiconductive source/drain regions of one conductivity type having a semiconductive channel region of opposite conductivity type therebetween. A gate construction is received over the channel region. Current can be caused to flow between the source/drain regions through the channel region by applying a suitable voltage to the gate.
The channel region is in some cases composed of background doped bulk semiconductive substrate or well material, which is also received immediately beneath the opposite type doped source/drain regions. This results in a parasitic capacitance developing between the bulk substrate/well and the source/drain regions. This can adversely affect speed and device operation, and becomes an increasingly adverse factor as device dimensions continue to decrease.
The invention was principally motivated in overcoming problems associated with the above-identified parasitic capacitance in bulk field effect transistor devices. However, the invention is in no way so limited, nor limited to solving or reducing this or any other problem whether identified/identifiable herein or elsewhere, with the invention only being limited by the accompanying claims as literally worded and as appropriately interpreted in accordance with the doctrine of equivalents.
SUMMARY
This invention includes methods of forming field effect transistors, methods of forming integrated circuitry, and integrated circuitry. In but one implementation, a method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions.
In one implementation, a method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material.
In one implementation, integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region.
In one implementation, integrated circuitry includes a substrate having a field effect transistor formed thereon. The transistor includes a gate, a channel region, and source/drain regions on opposing sides of the channel region. First and second dielectric insulative material masses are received beneath and contact the source/drain regions. The dielectric insulative material masses do not extend to beneath the channel region.


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