Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-04-19
2003-03-18
Sherry, Michael (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C324S765010
Reexamination Certificate
active
06535009
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a configuration for carrying out burn-in processing operations of semiconductor devices at the wafer level. More specifically, a semiconductor wafer containing a multiplicity of semiconductor chips is subjected to a burn-in operation that subjects the integrated circuits and components produced in the semiconductor chips to externally supplied voltages at a raised temperature.
Burn-in processing operations for semiconductor devices, such as chips, produce artificial aging in the latter. Such artificial aging puts the semiconductor device in a state which it would otherwise not attain until after a relatively long period of operation. This allows all those semiconductor devices found to be faulty after burn-in to be picked out following the burn-in operation. In other words, a burn-in operation makes it possible to discard such semiconductor devices before they are fitted in appliances that would otherwise fail after the aforementioned relatively long period of operation.
During a burn-in operation, semiconductor devices are subjected to particular loading tests at raised temperatures, for example 140° C., by impressing predetermined voltage patterns on the semiconductor device. Thus, for example, dynamic random access memories (DRAMs) can be subjected to cyclic loading of the word lines (“word line cycling”).
Burn-in processing operations are thus indispensable in practice, when customers are to be supplied with semiconductor devices whose reliability is ensured over a long period of operation. The burn-in processing operations make it possible to pick out semiconductor devices which may be developing faults before they are supplied to customers, so that the occurrence of faults after the semiconductor devices are fitted into the intended appliances can be prevented.
To date, burn-in processing operations have been carried out only at chip level and not at wafer level. In a burn-in operation for a chip, voltage must be applied to defined connections for the chip using approximately 60 connections, and probe cards having more than 1500 needles are currently not available. A wafer having approximately 1000 chips, however, which would require probe cards having approximately 60,000 needles for burn-in processing at the wafer level. This requirement is more than an order of magnitude above the currently available probe cards having approximately 1500 needles.
Burn-in processing operations at the chip level are encumbered by particular disadvantages, which is why there has for a long time been a considerable demand for burn-in at the wafer level. These disadvantages can be summarized as noted below. First, with burn-in at the chip level, the semiconductor devices are cast in plastic. If faults are detected after the burn-in operation, they cannot be repaired. This is particularly disadvantageous in the case of memory devices, for example, such as DRAMs, with redundant circuits which could in essence be activated using laser fusing, or burning through fuses, to replace cells which have failed, and hence to carry out repair. However, detected faults can be repaired in this way only if the chip has not yet been encased in plastic or another casing. Second, a conventional burn-in operation requires components to be fitted into separate holders with which contact is made during the burn-in operation. Such holders are frequently reused and subjected to high temperatures during the burn-in operation. This frequent reuse of the holders leads to contact problems of a general type, which can result in a reduction in the yield and, in all cases, necessitates frequent checking and conversion of burn-in boards or panels. Third, although burn-in processing operations are carried out, as far as possible, uniformly and in parallel, they occasion considerable equipment costs that can be attributed not least to the long burn-in times in the order of a few hours. Fourth, functional test programs are currently moved to the burn-in furnace as far as possible, since this allows complex test devices to be eliminated and product quality can be increased. As a result of the aforementioned parallel operation during burn-in, in which, as an example, 16 semiconductor devices are connected to the same address bus, signals are slow on account of the high capacitive load, which in turn has a negative effect on the processing time. It is also barely possible to register an individual faulty semiconductor device, since the information obtained merely indicates that one of the, by way of example, 16 semiconductor devices has a fault.
For the aforementioned reasons, repeated attempts have been made to begin burn-in processing operations at the wafer level (“wafer level burn-in” or “WLBI”). Therefore, during WLBI, burn-in takes place on the whole wafer before it is separated into the individual chips that are to be cast in plastic.
Since WLBI using probe cards is not possible for the aforementioned reasons, the below listed two possibilities have always been considered to date. Conventional contact-making methods are employed in which bonding wires of appropriate shape are used as thin probe needles. The wafer is then brought into contact with a board provided with such bonding wires.
In an unconventional procedure, a “Gore Mate” is used, for example, which is in essence made of an insulator incorporating thin metal balls made of gold, for example, which do not touch one another. If this “Gore Mate” is pressed between a wafer and an appropriately shaped contact structure, it can be assumed that the metal balls make points of contact, as long as the contact pads are of sufficient size and the spacing between the metal balls remains sufficiently small.
However, none of these previously conceived methods reliably enables burn-in processing operations to be carried out for semiconductor devices at the wafer level.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a configuration for carrying out burn-in processing operations of semiconductor devices at the wafer level that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which can be used simply and reliably at the wafer level.
With the foregoing and other objects in view there is provided, in accordance with the invention, in combination with a semiconductor wafer having a plurality of semiconductor chips, a configuration for carrying out burn-in processing operations of the semiconductor chips on the semiconductor wafer, the configuration has at least one built-in-self-test unit disposed in the semiconductor wafer for carrying out the. burn-in processing operations on the semiconductor chips, the burn-in processing operations subjecting the semiconductor chips to externally supplied voltages at an elevated temperature.
The invention achieves this object in a configuration of the type mentioned in the introduction with at least one BIST unit (BIST=“built-in self-test”) provided in the semiconductor wafer.
To date, BIST techniques have been used to produce self-test circuits for chips so that the test time can be reduced or circuits are obtained which test themselves automatically without requiring any additional complex external test equipment.
The present invention now advantageously applies the BIST technique at the wafer level by providing BIST configurations on the wafer which permit burn-in processing operations to be carried out. Thus, an essential feature of the present invention is the combination of BIST techniques with WLBI.
The general use of BIST techniques for WLBI is particularly advantageous because all the signals and patterns are produced on the wafer itself, and configurations which make full contact on the wafer, such as probe cards, can be dispensed with. In this case, for example, an individual BIST unit can be provided for each chip on the wafer or for a respective plurality of chips on the wafer. Such a unit can then supply the necessary control signals to one chip or to the plurality
Mayback Gregory L.
Nguyen Jimmy
Sherry Michael
LandOfFree
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