Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-12-04

2003-03-04

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230030, C365S189011, C365S230090

Reexamination Certificate

active

06529435

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device in which subblocks each constituted by one or two or more memory cells are arranged in matrix form.
(2) Description of the Related Art
In the so-called DRAM (Dynamic Random Access Memory), it is necessary to refresh the memory cells, and Ski conventionally, therefore, access from outside is temporarily halted to carry out refreshing.
If access from outside is temporarily halted, however, the time required to respond to the external access is correspondingly prolonged, which is inconvenient for applications requiring high-speed access.
The applicant hereof previously filed a patent application (Japanese Patent Application No. 2000-368423) relating to a, semiconductor memory device (hereinafter referred to as the semiconductor memory device of the prior application) which permits external access even during refreshing.
FIG. 22
illustrates the principle of operation of the semiconductor memory device of the prior application. As shown in the figure, the semiconductor memory device of the prior application comprises a memory array constituted by 16 subblocks, and a parity array constituted by four subblocks.
Each subblock comprises a cell array having memory cells arranged in matrix form, S/A's (Sense Amplifiers), and decoders.
The subblocks constituting the memory array store ordinary data, while the subblocks constituting the parity array store parity data.
FIG. 23
illustrates the operation for reading out data from the memory array. As shown in the figure, when data is read out, a series of subblocks (shaded subblocks) along a row is selected to read out data D
1
to D
4
.
FIG. 24
illustrates a refresh operation. In the semiconductor memory device of the prior application, the subblocks are refreshed one by one in sequence. In the illustrated example, the subblock
2
-
3
indicated by hatching is the target of refreshing. To explain the operation in more detail, a row of subblocks is refreshed from left to right, for example, and when all subblocks included in one row have been refreshed, the next row is refreshed.
FIG. 25
illustrates an operation performed when a subblock to be refreshed overlaps with the subblocks from which data is read out in the case where refresh operation and data read operation are carried out in parallel with each other.
In the illustrated example, the subblocks
2
-
1
to
2
-
4
in the memory array are the target of data read, and the subblock
2
-
3
is the target of refreshing.
In this case, data cannot be read from the subblock
2
-
3
, and therefore, the semiconductor memory device of the prior application is configured such that data output from the subblocks
2
-
1
,
2
-
2
and
2
-
4
and parity data read from the subblock
2
P are supplied to a data restoration circuit
200
to restore data of the subblock
2
-
3
based on these items of data.
With this method, however, since the subblocks are refreshed one by one, a problem arises in that the amount of power consumption is large, compared with the case where the entire memory array is collectively refreshed, for example.
SUMMARY OF THE INVENTION
The present invention was created in view of the above circumstances, and an object thereof is to provide a semiconductor memory device which permits access even during refresh operation and also is low in power consumption.
To achieve the object, there is provided a semiconductor memory device in which subblocks each constituted by one or two or more memory cells are arranged in matrix form. The semiconductor memory device comprises an address input circuit for receiving an input address, a readout circuit for reading out data from at least part of a subblock group arranged in a column or row direction and specified by the address input via the address input circuit, and a refresh circuit for refreshing at least part of a subblock group arranged in a row or column direction and intersecting with the subblock group from which data is read out by the readout circuit.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.


REFERENCES:
patent: 5550781 (1996-08-01), Sugawara et al.
patent: 5822264 (1998-10-01), Tomishima et al.
patent: 6233181 (2001-05-01), Hidaka
patent: 2000-368423 (2000-04-01), None

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