Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-04-13
2003-09-09
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S601000, C438S612000, C438S754000, C438S978000, C438S713000
Reexamination Certificate
active
06617234
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90108258, filed on Apr. 6, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing semiconductor. More particularly, the present invention relates to a method of forming metal fuse and bonding pad.
2. Description of Related Art
In the manufacturing of semiconductor memory, some or even one defective memory cell in an integrated circuit will render the entire chip defective. In general, a densely packed integrated circuit will produce more device defects than a loosely packed integrated circuit. Hence, as the level of integration increases, yield of the semiconductor product may drop correspondingly.
To increase the yield of semiconductor production, redundancy circuits are often added to the integrated circuit. The redundancy circuits, besides serving as a memory array for holding binary data, also provide redundant memory cell for substituting defective memory cells. The redundant memory cells are connected to word lines and bit lines respectively. If several thousand memory cells in the main memory cell array are found to be defective after circuit testing, all the defective memory cells can be replaced by the redundant memory cells so that a faultless memory chip is produced.
A memory circuit, besides having a normal memory cell array, further includes a standby memory cell array (or redundant memory cell array) for substituting defective memory cells when required. In general, main memory cell array and the redundant memory cell array are interconnected through fuses. When a defective memory cell needs to be replaced, the particular fuse leading to the defective cell is cut. To reduce cost and complexity in application as the level of integration increases, metal fuses are formed on the uppermost layer of the semiconductor device. In other words, the metal fuses and the bonding pad are often formed on the same layer.
Conventionally, the metal fuses and the bonding pads are formed on the same layer by forming a metallic layer over a substrate and then patterning the metallic layer so that the metal fuses and the bonding pads are formed concurrently. However, in general, a thick bonding pad and a thin metal fuse are preferred. Consequently, conflicting considerations have to be resolved if metal fuses and bonding pads are required to form on the same metallic layer. For example, a relatively thin metallic layer must be formed if easily cut metal fuses are required after patterning. On the other hand, thickness of the bonding pads is restricted by subsequent wire bonding because insufficient bonding pad thickness often leads to pad-joining problems.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of forming metal fuse and bonding pad with due considerations to bonding pad requirements.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming metal fuse and bonding pad. A conductive layer is formed in a substrate. A dielectric layer is formed over the substrate. The dielectric layer has an opening that exposes a portion of the conductive layer. A metallic layer is formed over the dielectric layer. The metallic layer is patterned to form a metal fuse and a bonding pad. The bonding pad is electrically connected to the conductive layer via the opening. Both the metal fuse and the bonding pad have undercut sidewalls. Spacers are formed on the undercut sidewalls of the metal fuse and the bonding pad. Finally, a passivation layer that exposes the metal fuse and the bonding pad is formed over the substrate.
In this invention, metal fuses and bonding pads are formed on the same layer so that production cost and manufacturing complexity are reduced. In addition, thicker bonding pads are produced thereby increasing the bondability of wire in subsequent wire-bonding step. Furthermore, the metal fuses have undercut sidewalls. Hence, width of each metal fuse is narrower and burning is quicker. The presence of spacers over the undercut sidewalls also prevents horizontal sputtering of metal while the metal fuse is burnt. Thus, bridging between metal fuses is avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5053849 (1991-10-01), Izawa et al.
patent: 5578166 (1996-11-01), Hirota
patent: 5607877 (1997-03-01), Matsuda et al.
patent: 5798819 (1998-08-01), Motsiff
patent: 5858869 (1999-01-01), Chen et al.
patent: 6358831 (2002-03-01), Liu et al.
Hsiung Chiung-Sheng
Huang Yimin
Wang Sung-Hsiung
Fourson George
J.C. Patents
Maldonado Julio J
United Microelectronics Corp.
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