Semiconductor device with sidewall spacers and elevated...

Details Semiconductor device with sidewall spacers and elevated... Semiconductor device with sidewall spacers and elevated...

2001-09-19

2003-09-09

Elms, Richard (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S383000, C257S387000, C257S388000, C438S300000

Reexamination Certificate

active

06617654

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device such as Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with a reduced size, and also relates to a method of manufacturing such a semiconductor device.
2. Description of the Related Art
FIG. 14
is a cross sectional view illustrating a conventional MOSFET having an extension structure described, for example, in Silicon Processing for the VLSI Era Volume 2, Process Integration, page 354 to 356. In the literature, this is called as an LDD (Lightly Doped Drain) structure and has also been called in recent years as an extension structure along with increasing its concentration of impurities. In the figure, reference numeral
1
denotes a p-type silicon substrate;
2
, a device isolation region;
5
, a gate insulating film;
6
, an n-type polysilicon gate electrode;
9
, extension regions;
10
, side walls;
13
a,
a drain region of source/drain regions;
13
b,
a source region of the source/drain regions;
14
, a depth of junction of the source/drain regions;
15
, a depth of junction of extension regions;
16
,
17
, silicide regions;
24
, a depletion layer formed by the drain region;
25
, a depletion layer formed by the source region.
A device structure and a manufacturing method of MOSFET having the conventional extension structure are to be explained briefly below.
At first, device isolation regions
2
for isolating active regions from the other ones are formed in the p-type silicon substrate
1
. Boron, BF
2
or the like as p-type impurity are ion implanted to form a well (not illustrated). Then, a gate insulating film
5
and an n-type polysilicon film are deposited on the surface of the p-type silicon substrate
1
. A gate electrode pattern is formed by photolithography, and etching is conducted using the pattern as a mask to form an n-type polysilicon gate electrode
6
.
Successively, phosphorus, arsenic or the like as an n-type impurity is ion implanted to form extension regions
9
in a self-aligned manner. Then, side walls
10
are formed with a silicon oxide film, a silicon nitride film, or the like. Phosphorus, arsenic, or the like as an n-type impurity is ion implanted. Thereafter, heat treatment is applied to form n-type source/drain regions
13
, which are then salicided to form the silicide region
16
in the gate electrode and the silicide region
17
in the source/drain regions, thereby completing a main portion of MOSFET.
For further improving the degree of integration of the transistor, it is necessary to reduce the size of individual MOSFETs and, as one of means for reducing the size, it is effective to reduce the thickness of the side walls
10
.
However, in the prior MOSFET, since the junction
14
of the source/drain regions
13
is deeper than the junction
15
of the extension regions
9
from the surface of the silicon substrate
1
, the source/drain regions
13
cover the extension regions
9
entirely, decreasing the thickness of the side walls
10
, as shown in FIG.
15
. As a result, the depletion layer
24
formed by the drain region
13
a
influences the source region
13
b
. The interval between the depletion layer
25
and the depletion layer
24
shortens from the distance
1
in the device structure with the thick side walls
10
in
FIG. 14
to the distance
2
in the device structure with the thin side walls
10
in
FIG. 15
, increasing the operation voltage of the MOSFET. Such a short interval easily produces the short channel effect.
In view of the above, as a countermeasure, it may be considered to reduce the influence of the junction in the source/drain regions by making the depth of junction
14
of source/drain regions
13
shallower. However, when the depth of junction
14
is merely made shallow, since the entire thickness of the source/drain regions
13
is reduced, this results in the disadvantage of increasing the source/drain resistance.
SUMMARY OF THE INVENTION
This invention intends to reduce the size of the semiconductor device by decreasing the thickness of the side walls while preventing the disadvantage described above.
A semiconductor device according to this invention comprises: a gate electrode formed, through a gate insulating film, on a substrate of a first conductivity type; side walls formed on both lateral sides of the gate electrode; extension regions formed by introducing and diffusing impurity of a second conductivity type on both sides of the gate electrode in the substrate and having a predetermined depth of junction from the surface of the substrate; and source/drain regions composed of both an epitaxial growth film selectively grown on the substrate of the both sides of the gate electrode and regions introducing and diffusing impurities of a second conductivity type below the epitaxial growth film having a depth of junction identical with or shallower than the depth of junction of the extension regions. This can be provide an effect of reducing the size of MOSFET as a result that the thickness of the side walls can be reduced while keeping the excellent short channel effect and the low source/drain resistance.
A method of manufacturing a semiconductor device according to the invention has the steps of: forming a multi-layered film so as to form a gate electrode on a substrate of a first conductivity type and etching the multi-layered film to a predetermined pattern; forming side walls on both lateral sides of the gate electrode; introducing and diffusing impurities of a second conductivity type on both sides of the gate electrode in the substrate and conducting ion implantation of impurities of the second conductivity type and heat treatment under predetermined conditions so as to form extension regions having a predetermined depth of junction from the surface of the substrate; selectively forming an epitaxial growth film by an epitaxial growth method so as to form a portion of the source/drain regions on the substrate of both lateral sides of the gate electrode; conducting ion implantation of impurities of a second conductivity type in the substrate below the epitaxial growth film and heat-treating under predetermined conditions so as to form another portion of the source/drain regions having a depth of junction identical with or shallower than the depth of junction of the extension regions. This can provide an effect capable of efficiently manufacturing a semiconductor device with reduced size of MOSFET while keeping the excellent short channel effect.


REFERENCES:
patent: 5710450 (1998-01-01), Chau et al.
patent: 6346447 (2002-02-01), Rodder
patent: 6391692 (2002-05-01), Nakamura
Gwoziecki et al., “Suitability Of Elevated Source/Drain For Deep Submicron CMOS”, Proceeding of the 29thSolid-State Device Research Conference, Belgium, Sep. 1999, pp. 384-387.

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