Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-14
2003-03-18
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06536024
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the design of integrated circuits having clock signal distribution networks (clock trees) and clock gating circuitry, and more particularly to methods for making energy efficient integrated circuits (IC) with gated clock trees.
BACKGROUND OF THE INVENTION
Typical integrated circuit (IC) chips may contain hundreds of thousands or millions of transistor elements, plus wires and other elements such as resistors and capacitors to implement their logical functions. Additionally, an IC chip may contain a “clock tree” or “clock net,” comprising a network of wires and buffers and clock gating elements, that distributes and/or restricts the “clock signal” that controls the timing and operation of portions of the logical elements of the IC. When designing integrated circuits, a netlist description (model) of the integrated circuit is generated. The netlist includes a description of the integrated circuit's logical components and the connections or networks (“nets”) between the components. The components include all those circuit elements necessary for implementing the logic circuit, such as combinational logic (e.g. gates) and sequential logic (e.g., flip-flops and latches). The logic elements and other circuits controlled by a clock signal such that they add capacitance to the clock tree are generally referred to herein as “clock sinks” or “sinks.” The sequential logic elements (i.e., sinks), such as flip-flops, RAMs, dynamic logic gates, and latches, that are “clocked” by the clock structure of the circuit are usually described in the netlist, although their connections with the clock tree are usually omitted from the netlist during placement in the related art. The netlist descriptions of the related art generally do not include a description of the clock tree components, connections or nets for logic circuit placement decision purposes. The physical design process of integrated circuits has been traditionally performed in three separate operations: logic placement; clock tree optimization; and wiring. Traditionally, placement is the assignment of logic circuits in the netlist to locations (called “cells” or “bins”), on the chip image. Traditionally, the connections within clock trees, such as clock signal connections to clock buffers, clock gates, and clock sinks are only “optimized after placement” of the logic circuits has been completed. See, e.g., CIRCUIT PLACEMENT, CHIP OPTIMIZATION, AND WIRE ROUTING FOR IBM IC TECHNOLOGY, IBM Journal of Research and Development, (Volume 40, Number 4, July 1996). Wiring is the generation of routes between circuit elements, using the available interconnection layers, to complete the connections specified in the final netlist.
The clock signal is the most fundamental control signal in a digital circuit, and is usually required to be transmitted to all regions of the IC chip that it controls. Buffers are generally used in the clock signal distribution tree to amplify and retransmit the clock signal where long thin wires spanning the IC chip would otherwise tend to slow or attenuate the propagation of the clock signal. As the rapidly developing field of low power integrated circuitry advances, the number of transistor logic elements per unit of chip surface area continues to increase. As the integrated circuit density on a chip increases, the amount of power consumed and heat generated per unit of area by the integrated circuits on the substrate increases proportionally. The integrated circuit industry has changed from TTL to Complimentary Metal Oxide Semiconductor (CMOS) technology in order to decrease the current consumption, thereby reducing power consumption and heat generation. CMOS logic circuits consume power when they are switched between logical states, such as by a clock signal. The power consumption of CMOS elements decreases in proportion with a decrease in switching frequency.
In typical Integrated Circuit (IC) designs, e.g., Application Specific Integrated Circuit (ASIC) or microprocessor designs, the clock signal distribution network or “clock tree” of the related art can consume from 20% to 80% of an integrated circuit's total active power. As the clock signal and its related circuitry may be a large power consuming factor within most microprocessor systems, one important technique for reducing power consumption in microprocessor designs is to reduce the power consumption of a microprocessor's clock signal distribution network (e.g., “tree”) by splitting the clock signal into several separate clock signals that can be individually disabled or “gated off” when the logical portion (e.g., “domain”) of the circuit it controls does not need to be clocked. The logical portion of the circuit that is controlled by the clock signal that is gated off by a particular clock gating signal is called a “clock gate domain” or “domain.”
The process known as “clock gating”, disables the clock signals fed to logic blocks (i.e., “domains”) of the circuit when the logic blocks (i.e., domains) are not currently in use by the circuit (e.g., microprocessor). Without clock-gating, power is consumed by every sink during every clock cycle. Power consumption due to the clocking of logic blocks that are not directly involved with the current operation of the microprocessor may be reduced by clock gating. Clock gating techniques of the related art require additional logic (e.g., clock gating logic) circuitry to generate the clock gating signals and also gates within the clock tree to gate the clock signal in each domain.
If a plurality of logically non-equivalent gated clock domains overlap the same physical region of the chip, the total clock tree capacitance can increase substantially, due to the overlapping and separate clock-gating circuitry and domain wiring. This increased capacitance can increase power consumption so much that any reduction due to clock gating is cancelled out. Conversely, if the sinks gated by a particular gated clock signal are forced into an exclusive physical region not overlapping any region occupied by the sinks controlled by other gated clocks, clock tree capacitance may be reduced, but significant skew, delay or wireability problems may be created.
In order to have a power savings, the clock gating logic circuitry must consume less power than is saved by gating the clock signals off. Therefore, net reduction of power consumption by clock gating is a balancing function of the power consumed by the added clock gating circuitry and wires and the power that would be consumed by leaving a domain or a subdomain (i.e., a portion of a domain) of the clock tree either ungated or less than maximally gated.
Strategies for defining logic blocks (i.e., “clock gate domains”) that can be clock-gated and strategies for identifying and/or generating the clock gating control signals that perform the clock gating are known to persons skilled in the art. The ideal clock signal distribution tree has the smallest number of clock gates that yield the maximum amount of clock gating power savings when running typical application code. The degree of optimization of clock distribution trees is generally limited in the related art by the constraints imposed by logic circuit placement that has been completed without regard for clock tree optimization considerations.
Traditionally, the connections and nets within the clock tree have been zero-weighted or omitted in models and/or placement netlists so that those connections and nets do not influence the placement of clock sinks or other logic circuits. Traditionally, clock optimization tools are employed only after placement, to perform optimization of clock tree nets, such as by gating the nets of domains and/or subdomains, interchanging sinks of equivalent nets, creating and moving parallel copies of clock buffers and/or gates, adding load circuits to balance clock net loads, and generating balanced clock tree routes. In general, the clock-gating strategies of the related art attempt to optimize clock tree structures by intelligently dist
Kotulak Richard M.
Schmeiser Olsen & Watts
Siek Vuthe
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