Semiconductor memory device with reduced number of redundant...

Details Semiconductor memory device with reduced number of redundant... Semiconductor memory device with reduced number of redundant...

2002-04-11

2003-05-20

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700

Reexamination Certificate

active

06567324

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of replacement of a defective memory cell by a redundant memory array.
2. Description of the Background Art
In recent years, a semiconductor memory device generally includes a redundant memory array, and even if a defect occurs in a part of memory cells in the manufacturing process, a memory array near the defective part of the memory cells is replaced by the redundant memory array to relieve the device.
FIG. 11
is a schematic diagram showing the configuration of a semiconductor memory device
500
including a conventional redundant memory array.
Referring to
FIG. 11
, conventional semiconductor memory device
500
includes memory banks BANK
0
to BANK
3
that can operate independently.
Memory bank BANK
0
includes a memory cell array
504
having column selecting line YS
00
in which a plurality of normal memory cells are arranged, and a redundant memory array
506
having spare column selecting line SYS
0
in which a plurality of spare memory cells are arranged.
Memory bank BANK
1
includes a memory cell array
514
having column selecting line YS
10
in which a plurality of normal memory cells are arranged, and a redundant memory array
516
having spare column selecting line SYS
1
in which a plurality of spare memory cells are arranged.
Memory bank BANK
2
includes a memory cell array
524
having column selecting line YS
20
in which a plurality of normal memory cells are arranged, and a redundant memory array
526
having spare column selecting line SYS
2
in which a plurality of spare memory cells are arranged.
Memory bank BANK
3
includes a memory cell array
534
having column selecting line YS
30
in which a plurality of normal memory cells are arranged, and a redundant memory array
536
having spare column selecting line SYS
3
in which a plurality of spare memory cells are arranged.
Semiconductor memory device
500
further includes redundancy determining circuits
502
,
512
,
522
and
532
activating redundant memory arrays
506
,
516
,
526
and
536
, respectively, in accordance with an address signal ADR.
It is noted that a redundant memory array often includes a row-related redundant memory array mainly relieving a word line from defectiveness and a column-related redundant memory array mainly relieving a bit line from defectiveness, and
FIG. 11
shows the case with the column-related memory array as a representative.
As shown in
FIG. 11
, conventional semiconductor memory device
500
including redundant memory arrays was provided with redundancy determining circuits of the number corresponding to that of the redundant memory arrays. Moreover, each redundancy determining circuit was often arranged in the vicinity of a corresponding redundant memory array.
If a defect occurs in a memory cell column selected by a column selecting line YS
00
, in response to an input of address signal ADR corresponding to the defective memory cell column, the redundancy determining circuit activates a spare column selecting line SYS
0
in place of column selecting line YS
00
. Thus, input data is stored in the redundant memory array. It is noted that a decoder selecting a normal column is inactivated at that moment.
Therefore, it is required for the redundancy determining circuit to store an address of a defective memory cell in a non-volatile manner. As a means therefor, e.g. a fuse element is often used. The fuse element is blown off by a laser beam or the like. In order to ensure disconnection and to avoid harming the adjacent elements, the fuse element must have a certain size, and no other elements should be arranged around the fuse element. Hence, as the number of provided redundant memory arrays becomes larger, the redundancy determining circuit occupies a larger area on a chip.
In a recent dynamic random access memory (DRAM) with a large capacity and increased operation speed, a memory array is divided into a plurality of banks, and control thereof has become complicated. For example, while redundant memory arrays and redundancy determining circuits that are dispersed in the banks can also be collectively arranged at one place so as to be used for a defect occurred in any bank, the redundant memory cell array may desirably be configured to share a word line or bit line with a normal memory cell when the operation speed is given a high priority. This is because a signal delay of the word line or bit line can be disregarded in such a case.
Though the redundancy determining circuits are provided corresponding to the redundant memory arrays respectively, as described earlier, only a part of the redundancy determining circuits is used per chip for relieving the device from defectiveness when a defective portion actually occurs in the conventional configuration.
The redundancy determining circuit has a fuse element or the like having a large area used for setting an address. This has caused a problem in that unused redundancy determining circuits occupy a large area on the chip.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device in which increase of a chip area occupied by redundancy determining circuits is alleviated by sharing only the redundancy determining circuit portion to reduce the number of the redundancy determining circuits.
According to an aspect of the present invention, a semiconductor memory device includes n memory regions, n selecting circuits, n control buses and a setting circuit (n is a natural number equal to or higher than 2).
Each of the n memory regions includes a normal memory region, and a replacement region replacing a partial region of the normal region when an operation failure is found in the partial region.
The n selecting circuits are provided respectively corresponding to the n memory regions, and each select the replacement region instead of the partial region in accordance with selection information.
The n control buses transmit the selection information to the n selecting circuits, respectively. The setting circuit holds, when specific information indicating a partial region is set, the specific information in a non-volatile manner, and compares an input address signal with the specific information, to output the selection information.
The setting circuit includes m program sets setting m pieces of the specific information, respectively, and m bus selecting and outputting circuits selecting any one of the n control buses and outputting the selection information (m is a natural number equal to or higher than 1).
Therefore, a main advantage of the present invention is that, since the bus selecting and outputting circuits are provided respectively corresponding to the memory regions to select a control bus and to output the selection information, the number of program sets can be determined irrespective of the number of memory regions or replacement regions and therefore the number of program sets can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5625596 (1997-04-01), Uchida
patent: 6011735 (2000-01-01), Ooishi et al.
patent: 6349064 (2002-02-01), Nakaoka
patent: 6411556 (2002-06-01), Amano
patent: 6438044 (2002-08-01), Fukuda
“Redundancy Techniques for High-Density DRAMs”, Masashi Horiguchi, 1996 Innovative Systems in Silicon Conference, pp. 22-29.

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