Memory device having an internal register

Details Memory device having an internal register Memory device having an internal register

2000-05-23

2003-04-01

Ellis, Kevin L. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000

Reexamination Certificate

active

06542976

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to digital storage devices, and more specifically, to dynamic random access memory.
BACKGROUND OF THE INVENTION
Improvements in fabrication technology have resulted in dynamic random access memories (DRAMs) with increased density, faster performance, and higher operating frequencies. Because overall memory bandwidth requirements are rising and the number of DRAMs in a system is falling, the ability to quickly transport data to and from each DRAM has become increasingly important. ASYNCHRONOUS DRAMS
In conventional memory systems, the communication between a memory controller and DRAMs is performed through asynchronous communications. For example, the memory controller uses control signals to indicate to the DRAM when requests for data transactions are sent. The data transfers themselves are also performed asynchronously. To meet increased speed requirements, various enhanced asynchronous memory systems have been developed. One such system is the Extended Data Out (EDO) DRAM memory system.
FIG. 1
is a block diagram illustrating a typical EDO DRAM system
100
. In the EDO DRAM system
100
, data transfers are performed asynchronously in response to control signals and addresses sent from pin buffers
116
of a memory controller to pin buffers
118
of the EDO DRAM over a plurality of lines
120
,
122
,
124
,
134
and
136
. Specifically, lines
122
carry an address that is stored in latches
112
and
114
. Line
120
carries a row address strobe ({overscore (RAS)}) that controls when the address stored in latch
112
is sent to row decoder
106
. Line
134
carries an output enable signal that controls data output of the DRAM. Line
136
carries a write enable signal that controls timing chains
108
and the direction of data flow on the bi-directional data bus
126
.
Upon receiving an address, row decoder
106
loads data that corresponds to the address from a memory array
110
in memory core
102
into a sense amplifier array
130
. Line
124
carries a column address strobe ({overscore (CAS)}) that controls when the address stored in latch
114
is sent to column decoder
104
. For a read operation, the column decoder
104
causes the data that is stored in the columns of the sense amplifier array
130
that correspond to the address received by column decoder
104
to be transferred through column I/O circuits
132
. The data passes through the column I/O circuits
132
to the memory controller over a data bus
126
.
Alternately, an EDO DRAM may use address transition detect circuitry to initiate the retrieval of data from the memory core, rather than the {overscore (CAS)} signal. Address transition detect circuitry is circuitry that monitors the address bus to detect transitions in the data that is being sent on the address bus. When a transition is detected, the EDO DRAM restarts the timing chains causing data corresponding to a new address to fall out of the column I/O circuits
132
.
The communication between the EDO DRAM and the memory controller is asynchronous. Thus, the EDO DRAM is not driven by an external clock. Rather, timing chains
108
that are activated by the {overscore (RAS)} and {overscore (CAS)} control signals are used to control the timing of the data transfer. Because the core
102
is not driven unless activated by the {overscore (RAS)} and {overscore (CAS)} control signals, the core
102
does not consume energy unless a data transfer operation is taking place. Therefore, the EDO DRAM consumes less power than alternative architectures in which the interface is clocked even when no memory operation is being performed.
FIG. 2
is a timing diagram for a read operation in EDO system
100
. At time TO the memory controller places on lines
122
an address that indicates the bank and row from which data is to be read. At time T
1
the {overscore (RAS)} signal goes LOW causing the address to be sent from latch
112
to row decoder
106
. In response, row decoder
106
causes the appropriate row of data to be transferred from memory array
110
to sense amplifier array
130
.
At time T
2
the memory controller places on lines
122
the address of the column from which data is to be read. At time T
3
the {overscore (CAS)} signal goes LOW causing the address to be sent from latch
114
to column decoder
104
. In response, column decoder
104
sends through column I/O circuits
132
data from the selected column of the row stored in sense amplifier array
130
. Assuming that {overscore (WE)} is HIGH and {overscore (OE)} is LOW, the data will appear on data bus
126
. The data on the data bus
126
takes some time to stabilize. To ensure an accurate reading, the memory controller does not read the data from the data bus until time T
4
.
The delay between the time at which the {overscore (RAS)} signal goes LOW to initiate a read operation and the time at which the data may be read from the data bus
126
is identified as t
RAC
. The delay between the time at which the {overscore (CAS)} signal goes LOW for a read operation and the time at which the data may be read from the data bus
126
is identified as t
CAC
. The delay between the time at which the column address is placed on the address bus and the time at which the data may be read from the data bus
126
is identified as t
CAA
. In a typical EDO DRAM, exemplary times are t
CAC
=15 ns and t
CAA
=30 ns.
In one variation, the memory controller is allowed to have column address flow through. The memory controller therefore has until T
3
(the fall of {overscore (CAS)} ), rather than until T
2
(the transmission of the column address), to decide whether to perform a given transaction. In the exemplary times above, the memory controller would have 15 ns more time to decide whether to perform a given transaction.
SYNCHRONOUS DRAMS
DRAMs built with an asynchronous RAS/CAS interface have difficulty meeting the high memory bandwidth demands of many current computer systems. As a result, synchronous interface standards have been proposed. These alternative interface standards include Synchronous DRAMs (SDRAMs). In contrast to the asynchronous interface of EDO DRAMS, SDRAM systems use a clock to synchronize the communication between the memory controller and the SDRAMs. Timing communication with a clock allows data to be placed on the DRAM output with more precise timing. In addition, the clock signal can be used for internal pipelining. These characteristics of synchronous communication results in higher possible transfer rates.
FIG. 3
is a block diagram illustrating a conventional SDRAM system
300
. In system
300
, the memory controller includes a plurality of clocked buffers
304
and the SDRAM includes a plurality of clocked buffers
306
. Data from control line
310
and an address bus
312
are received by a finite state machine
308
in the SDRAM. The output of the finite state machine
308
and the address data are sent to memory array
302
to initiate a data transfer operation.
FIG. 4
is a timing diagram that illustrates the signals generated in system
300
during a read operation. At time T
0
the memory controller places a read request on line
310
and an address on bus
312
. At time T
1
the SDRAM reads the information on lines
310
and
312
. Between T
1
and
12
the SDRAM retrieves the data located at the specified address from memory array
302
. At time T
2
the SDRAM places data from the specified address on data bus
314
. At time T
3
the memory controller reads the data off the data bus
314
.
Because system
300
is synchronous, various issues arise that do not arise in asynchronous systems. Specifically, the synchronous system has numerous pipeline stages. Unbalanced pipeline stages waste computational time. For example, if a shorter pipeline stage is fed by a longer pipeline stage, there will be some period of time in which the shorter pipeline stage remains idle after finishing its operation and before receiving the next set of data from the preceding pipeline stage. Similarly, if a short pipeline stage feeds a

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