Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-07-28
2003-09-02
Le, Don (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S010000, C326S038000
Reexamination Certificate
active
06614260
ABSTRACT:
BACKGROUND OF THE INVENTION
Although many advancements have been made in the area of semi-custom IC (integrated circuit) design and simulation technology, design errors, or “bugs,” are still, and probably always will be, a major concern for the IC designer. Several reasons exist for this situation. For one, although the speed and capability of simulation technology have improved greatly over the years, it is still not possible to provide 100 percent test coverage over all functions provided by an IC prior to chip fabrication, given the usual pressure to deliver the chip as soon as possible. No matter how fast a functional simulation can be performed, it can never rival the speed at which the actual IC will operate. Compounding the problem is the fact that ICs become faster and denser with each passing product generation, making the task of simulating the device even more difficult. The result of these particular circumstances is that a full-fledged functional test of the chip generally does not occur until the IC has been manufactured, at which time the tests are performed on an actual IC in real-time, thereby increasing both testing speed and coverage. It is at this point that many hard-to-find functional design errors are found. Unfortunately, with an error discovered at such a late date, the time-to-market of the IC is ordinarily negatively impacted since many functional errors require a new release of the chip.
Bugs are not the only instigators of unplanned design changes. For example, the functional specification for the chip may change after the device has been released to manufacturing. Such a change in the IC specification may be the result of a design change in the circuitry that is to communicate with the IC, thus necessitating a cooperating change in the IC. In other instances, the ultimate customer of the IC may request design changes based on new functional requirements. Therefore, it can be seen that several factors exist which may prompt IC design changes after the IC has already been released for fabrication.
In the past, the increase in time-to-market due to a functional design change in the IC has been mitigated somewhat by the placement of unused logic gates among the functional logic of the device. These extra gates can be connected to update the circuit in question by way of a “metal mask change,” whereby only the metal (connection) layers of the IC are modified. Generally speaking, changes involving only the metals layers are easier than those involving the silicon, thus slightly reducing the time involved with generating another release of the IC.
The value of metal-mask-only changes is evident, provided the associated design change has been proven. To actually prove the viability of the change in hardware prior to committing to another release of the IC for manufacture, however, has required other solutions. For example, many functional changes are implemented and verified by the use of a FIB (Fixed Ion Beam) machine. In general, a FIB is machine is capable of cutting and depositing metal on an existing IC to change the connections between circuit elements to implement the desired change. Although use of the FIB machine allows the correctness of a modification to be definitively proven, the unit is rather slow and tedious to use. As a result, the FIB process is not easily scalable to be used on multiple devices to expedite testing, nor is it practical to use the process multiple times on one device, which may be desirable in the case that a bug fix uncovers a more subtle functional error. Furthermore, many connection wires, such as those involving only the inner metal layers of the IC, cannot be operated on by the FIB machine due to their inaccessibility, with those wires often being covered by the connections that are implemented in the outer metal layers.
Therefore, a need currently exists in the integrated circuit industry for a quick and efficient way of implementing and verifying design modifications in IC devices. Additionally, it would be even more beneficial if it were possible to implement functional changes in multiple ICs rapidly, thereby allowing large quantities of ICs to be modified and tested concurrently. Such a method would also potentially eliminate the need to re-release the device in instances where only a limited number of ICs are to be produced initially.
SUMMARY OF THE INVENTION
Specific embodiments of the invention, to be presented below, provide a way for an IC designer to dynamically modify selected functions of an integrated circuit after fabrication. Physical alteration of the metal layers of the device is not employed. Furthermore, modifications of the functionality of the selected sections of the device can be performed on as many of the devices as is desired, and each IC may be updated multiple times with different modifications.
According to an embodiment of the invention, a block of programmable circuitry is coupled with the input and output signal lines of an original section of circuitry within the IC during the design phase. In this embodiment, the coupling of the output lines takes the form of one or more programmable interconnection blocks, so that either the original section of circuitry or the programmable circuit blocks may be connected with the output signal lines. Likewise, the input signal lines may be coupled to the programmable circuit blocks by way of programmable interconnection blocks, as well. Alternately, the input signals may be directly connected to the programmable interconnection blocks. Once it has been determined after IC fabrication that the original circuit section must be modified, the programmable circuit blocks and the programmable interconnection blocks may be configured dynamically, either within a dedicated IC test system, or the target system for which the IC was designed, thereby replacing the functionality of the original circuit section with that programmed into the programmable circuit blocks.
Alternately, a method according to an embodiment of the invention begins with coupling one or more programmable circuit blocks with the input signal lines of a section of circuitry that may be updated in the future. According to this method embodiment, the programmable circuit blocks are then coupled with one or more programmable interconnection blocks, which themselves couple the original circuit section with the output signal lines. Once the chip has been fabricated, the programmable circuit blocks are programmed to provide a new function to replace the functionality of the circuit section to be modified, and the programmable interconnection blocks are configured to connect the programmable circuit block to the output signal lines, which also has the effect of decoupling the problematic circuit section from the output signal lines.
Since the systems and methods of the present invention involve placing the appropriate programmable circuitry to allow future circuit changes, and the changes themselves merely involve programming the device electrically, no practical limit exists as to the number of times that a single IC may be updated, nor as to how many ICs are modified.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 5485102 (1996-01-01), Cliff et al.
patent: 5677884 (1997-10-01), Zagar et al.
patent: 6091258 (2000-07-01), McClintock et al.
Nuber Paul D
Welch M. Jason
Agilent Technologie,s Inc.
Le Don
Way Kyle J.
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