Semiconductor device and process for making the same

Details Semiconductor device and process for making the same Semiconductor device and process for making the same

2000-08-04

2003-01-21

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S627000, C438S628000, C438S637000, C438S687000

Reexamination Certificate

active

06509257

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and processes for making the same, and more particularly, to a semiconductor device employing copper for an upper layer wiring and a process of making the same. This application is a counterpart application of Japanese application Serial Number 11-297128 filed Oct. 19, 1999, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
In order to meet demands for high degrees of integration and density in semiconductor integrated circuits, submicron technology is applied to electrode wiring. Since the semiconductor integrated circuits require high speeds and low energy consumption, copper wiring is widely used in the submicron electrode wiring for its low resistance and high reliability.
One of the most popular methods of forming the copper wiring is a damascene process by which copper is deposited on an interlayer dielectric film so as to fill wiring grooves formed in the interlayer dielectric film, and polished and removed by chemical mechanical polishing (CMP) except for those in the wiring grooves. The copper is deposited usually by plating process which is superior to sputtering process in the burying characteristics and economy.
In order to simplify the damascene process for economy, a dual damascene process wherein wiring and conductive plugs are formed simultaneously draws attention. In the dual damascene method, wiring and conductive plugs are formed simultaneously with the same material by forming wiring grooves and via-holes or through-holes in an interlayer dielectric film, depositing copper on the film so as to fill the via- or through-holes, polishing away the copper film by the CMP process except for those in the wiring groove and via- or through-holes, thereby reducing the process time and cost.
However, the current sputtering process employed by the dual damascene process is so poor in burying characteristics that it is difficult to bury conductive material evenly in wiring grooves or via- or through-holes where the aspect ratio of the via- or through-holes between wiring lines is increased by submicron technology. Since it is comparatively easy to bury conductive material in the single damascene process, the use of the single damascene process to the manufacture by submicron technology of wiring lines for high-density, high-integration semiconductor devices is expected to increase.
In order to prevent copper from diffusing into the interlayer dielectric film upon deposition in the upper layer wiring grooves, a barrier layer of titanium nitride (TiN) or tantalum nitride (TaN) is formed by sputter process or the like on the upper layer wiring grooves prior to the copper deposition. Since the barrier layer is formed on the conductive plugs in the wiring grooves as well as the interlayer dielectric film surface, upper layer copper wires are formed via the barrier layer.
The film formation by CVD process for copper wiring has the problems of separation, impurity contamination, and high cost so that it is impractical to apply to the device manufacture. The film formed by sputtering process has comparatively poor covering property over the groundwork so that it is impossible to form films conformably. Thus, copper wiring is formed usually by plating process which has excellent burying characteristics. In this case, a copper seed layer must be formed by sputtering process, for example, to conduct electric current upon plating.
The process for forming tungsten (W) conductive plugs and upper-layer copper wires by the single damascene process for a double layer wiring structure will be described with reference to
FIGS. 13 and 14
. Alternatively, the W plugs may be replaced by copper plugs formed by plating process (hereinafter “plated Cu plugs”). FIGS.
13
(
a
)-(
c
) and
14
(
a
)-(
b
) show the manufacturing process of a semiconductor device.
In FIG.
13
(
a
), a dielectric film
1
and a stopper protective film (not shown) of silicon nitride (SiN) or the like are formed on a semiconductor substrate (not shown) on which predetermined elements are formed. Then, a lower layer wiring groove is formed by anisotropic etching such as reactive ion etching (RIE). Then, a metal, such as copper, is deposited on the entire surface so as to fill the lower layer wiring groove, forming a metal film, which is then polished by CMP, for example, until the stopper protective film is exposed, forming a lower layer wiring line
2
. Then, an interlayer dielectric film
3
and a stopper protective film
4
of SiN or the like are deposited successively on the dielectric film including the lower layer wiring line
2
.
Then, resist is applied to the stopper protective film
4
to form a resist film (not shown). Then, the stopper protective film
4
and the interlayer dielectric film
3
within a target area are removed by photolithography and etching to a predetermined line thickness to form a predetermined via- or through-hole.
Then, an adhesion layer
5
for CVD-W deposition is formed on the entire surface including the via- or through-hole, and a blanket CVD-W layer is deposited so as to fill the via- or through-hole. Then, the excessive CVD-W layer and the adhesion layer
5
on the stopper protective layer
4
are removed by CMP to form a W plug
6
.
In FIG.
13
(
b
), a first interlayer dielectric film
7
is deposited on the entire surface including the CVD-W layer, resist is then applied to form a resist film (not shown), and then photolithography and etching are applied to form an upper layer wiring groove
8
.
In FIG.
13
(
c
), a barrier layer, such as a TiN or TaN film, is deposited on the entire surface including the upper layer wiring groove
8
to prevent copper from diffusing into the interlayer dielectric film
3
from a copper line to be formed in the wiring groove
8
. Then, a seed layer is deposited to form a barrier/seed layer
9
as an electrode for depositing a plated-Cu film.
In FIG.
14
(
a
), a copper wiring film
10
is deposited by plating process on the entire surface so as to fill the upper layer wiring groove
8
in the barrier/seed layer
9
(hereinafter “plated Cu film”). Then, as shown in FIG.
14
(
b
), the plated Cu film
10
is polished by CMP process until the barrier/seed layer
9
and the interlayer dielectric film
7
are exposed so that the plated Cu film is left only in the upper layer wiring groove
8
, forming an upper layer copper wire
11
.
As shown in FIG.
14
(
b
), in the single damascene process there is the barrier/seed layer
9
between the upper layer Cu wire
11
and the W plug
6
to prevent diffusion of the copper so that electrical conduction is made through the barrier/seed layer
9
between the upper layer Cu wire
11
and the W plug
6
.
However, the resistivity of the barrier layer is
10
or more times higher than that of the Cu wire so that low resistance wiring material is used to reduce the wiring resistance. However, the parasite resistance of wiring is still very high. This considerably lowers the wiring characteristics and thus the device characteristics and, therefore, it is necessary to avoid the use of the high resistance film as a barrier layer between the wiring and the conductive plug for reducing the resistance of the entire wiring and keeping the device high performance. Especially, it is necessary in the highly integrated devices made by submicron technology using low resistance wiring materials.
SUMMARY OF THE INVENTION
The present invention is made to solve the above problems.
According to an aspect of the invention, there is provided a semiconductor device which comprises a ground layer having a surface at which surfaces of a dielectric film and a lower layer wiring line embeded in said dielectric film are exposed, a first interlayer dielectric film formed on the surface of the ground layer and having a via-hole formed therein such that the surface of the lower layer wiring line is exposed in the via-hole, a conductive plug formed in the via-hole and connected to the

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