Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-01-31
2003-05-27
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06571373
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the testing of computer system designs by software simulation, and more particularly to a verification methodology which provides portability across simulator types.
The complexity and sophistication of present-day integrated circuit (IC) chips have advanced significantly over those of early chip designs. Where formerly a chip might embody relatively simple electronic logic blocks effected by interconnections between logic gates, currently chips can include combinations of complex, modularized IC designs often called “cores” which together constitute an entire “system-on-a-chip”, or SOC.
In general, IC chip development includes a design phase and a verification phase for determining whether a design works as expected. The verification phase has moved increasingly toward a software simulation approach to avoid the costs of first implementing designs in hardware to verify them.
A key factor for developers and marketers of IC chips in being competitive in business is time-to-market of new products; the shorter the time-to-market, the better the prospects for sales. Time-to-market in turn depends to a significant extent on the duration of the verification phase for new products to be released.
As chip designs have become more complex, shortcomings in existing chip verification methodologies which extend time-to-market have become evident.
Typically, in verifying a design, a simulator is used. Here, “simulator” refers to specialized software whose functions include accepting software written in a hardware description language (HDL) such as Verilog or VHDL which models a circuit design (for example, a core as described above), and using the model to simulate the response of the design to stimuli which are applied by a test case to determine whether the design functions as expected. The results are observed and used to de-bug the design.
In order to achieve acceptably bug-free designs, verification software must be developed for applying a number of test cases sufficient to fully exercise the design in simulation. In the case of SOC designs, the functioning of both the individual cores as they are developed, and of the cores interconnected as a system must be verified. Moreover, a complete SOC design usually includes an embedded processor core; simulation which includes a processor core tends to require an inordinate amount of time and computing resources, largely because the processor is usually the most complex piece of circuitry on the chip and interacts with many other cores.
It can be appreciated from the foregoing that verification of an SOC can severely impact time-to-market, due to the necessity of developing and executing software for performing the numerous test cases required to fully exercise the design.
However, inefficiencies in current verification methodologies exacerbate time pressures. For example, unit-level (i.e., individual core as opposed to system-on-chip) verification is typically performed on an event simulator, which provides for ease in de-bugging a design but is comparatively slow, while the later SOC verification utilizes a cycle simulator for greater speed. Moreover, there are a variety of different commercially-available simulator types which are typically used in SOC design verification. When interpreting HDL to generate a software model of a design for simulation, each simulator type identifies constituent elements of a model, such as input or output signals or registers, according to a simulator-specific format. A test case which is applying stimulus to a particular model being simulated needs to communicate with the model in the format used by the particular simulator.
The need to adapt verification software for the transition from an event simulator to a cycle simulator and to communicate with a model being simulated in a simulator-specific format typically entails a coding effort which slows verification. Accordingly, it would be generally desirable in verification be able to design test cases and other verification software without being concerned for simulator-specific details, since this would enable faster, more efficient verification, portability across verification platforms, and, consequently, reduced time-to-market.
SUMMARY OF THE INVENTION
The present invention provides a method for performing simulator-independent verification of component cores of a SOC design. A simulator-independent environment is implemented in computer-executable instructions which allows for verification software to be easily portable across simulator types and verification stages. The simulator-independent environment interfaces between a test case generator and a specific simulator type being used to simulate a model (core), receives a request from the test case generator representing a stimulus to a design element in the model, and converts the stimulus into a simulator-specific form which may be applied to the model.
In an embodiment, the simulator-independent environment utilizes hierarchical data structures to organize simulator-specific information. Depending upon what kind of simulator is being used for a simulation session, corresponding functions in the simulator-independent environment are invoked to obtain simulator-specific information from files built during initialization, and used to access a design element in the simulated model in response to a request from a test case generator.
The simulator-independent environment further includes simulator-independent clock models corresponding to varying simulation clock frequencies. For a particular simulation session, a given clock model may be linked to a plurality of bus functional models to drive the bus functional models at the appropriate user-defined clock frequency. This allows a generalized bus functional model to be configured to run at any clock speed, simply by being associated with the appropriate clock model object.
REFERENCES:
patent: 5600579 (1997-02-01), Steinmetz, Jr.
patent: 5838948 (1998-11-01), Bunza
patent: 6052524 (2000-04-01), Pauna
patent: 6182258 (2001-01-01), Hollander
patent: 6240543 (2001-05-01), Bhandari
patent: 6249893 (2001-06-01), Rajsuman et al.
patent: 6269467 (2001-07-01), Chang et al.
Shah et al, “Target Processor and Co-Verification Environment Independent Adapter—A Technoligy to Shorten Cycle-Time for Retargeting T1 Processor Simulators in HW/SW Co-Verification Environments,” IEEE, Sep. 1999, pp. 37-41.*
Clement et al, “Fast Prototying: A System Design Flow Applied to a Complex System-on-Chip Multiprocessor Design,” IEEE, Jun. 1999, pp. 420-424.*
Bill Cordan, “An Efficient Bus Architecture for System-on-Chip Design,” IEEE, May 1999, pp. 623-626.*
Arnold S. Berger, “Applying Hardware/Software Co-Design to Systems-on-a-Chip,” IEEE, Sep. 1998, pp. 22-28.*
Chauhan et al, “Verifying IP-Core Based System-on-Chip Designs,” IEEE, Sep. 1999, pp. 27-31.*
Bulent Dervisoglu, “Design for Testability: It is Time to Deliver it for Time-to-Market,” IEEE, Sep. 1999, pp. 1102-1111.0.
Devins Robert J.
Kautzman Mark E.
Mahler Kenneth A.
Mitchell William E.
Connolly Bove & Lodge & Hutz LLP
Hume Larry J.
International Business Machines - Corporation
Kotulak Richard M.
Siek Vuthe
LandOfFree
Simulator-independent system-on-chip verification methodology does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Simulator-independent system-on-chip verification methodology, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Simulator-independent system-on-chip verification methodology will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3057357