Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-08-31
2003-07-01
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06588001
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of integrated circuits. More particularly, it relates to a method for automatically inserting repeater cells between functional blocks of a sub-micron design.
2. Description of the Related Art
The number of logic gates used in a deep sub-micron design is extraordinary compared to designs of just a few years ago. In today's chip designs, logic gates are grouped within functional blocks. There may be hundreds of thousands of logic gates within each functional block, and there may be many functional blocks that make up a single die.
There are a number of design tools that lay out a logic design onto a die. These tools are generally known as “floorplanning tools.” A floorplanning tool attempts to find the best placement of all the logic cells of a design, keeping the cells that communicate with one another close to each other. In this manner, the floorplanning tools form blocks of logic called functional blocks. These functional blocks make up the highest level of logical hierarchy on the die.
Experience has shown that for large designs, it is advantageous to floorplan the large functional blocks onto specific areas of the die through the use of fences. Fences keep all the logic cells of a particular functional block together in the same general area, as depicted in FIG.
1
.
FIG. 1
shows a die
100
that contains three functional blocks A, B, and C. Each of the functional blocks A, B, C, is contained within a respective fence
105
,
110
,
115
. Fencing prevents cells from a particular functional block from being scattered across the die, and will generate the best timing results within the fenced regions.
Floorplanning the large functional blocks A, B, C, solves many of the timing delay problems in a design, however, it also tends to worsen delays incurred in the interconnects
120
,
125
,
130
between the functional blocks A, B, C. Each of the functional blocks A, B, C communicate with each other on the die through control signals, etc. Therefore, interconnects
120
,
125
,
130
are required between the functional blocks A, B, C.
The interconnects (e.g., wires, traces, etc.)
120
,
125
,
130
may need to be long, traversing many microns across the die. In sub-micron designs, long interconnects traversing across the die will incur a substantial delay due to large RC (i.e., resistance×capacitance) values that impede a signal travelling from a source
135
to a destination
140
. These delays affect the maximum speed at which the entire chip may operate.
Turning to
FIG. 2
, it is known that inserting a repeater cell
200
within a length of interconnect (e.g.,
120
of
FIG. 1
) is advantageous to break up the long interconnect length, such that the source
135
drives a length of interconnect
203
and the repeater cell
200
drives a length of interconnect
205
. Repeater cell
200
allows a signal to propagate faster because long wires incur non-linear delays. The repeater cell
200
serves to boost the signal strength, allowing a signal to traverse larger distances with less propagation delay. One known repeater
200
configuration is two consecutive inverters
220
,
215
. Repeater
200
first inverts the control signal, then inverts it again to arrive at the original signal; however, the original signal is refreshed by the repeater
200
.
Due to the very large number of inputs/outputs (I/Os) (e.g.,
135
,
140
) between the functional blocks A, B, C in an actual die, manually inserting the repeater cells
200
(e.g., during the physical layout stage of manufacturing the die
100
) is very time consuming and prone to human error. One method for inserting repeaters
200
within long interconnect lines
120
is disclosed in U.S. Pat. No. 5,838,580 to Srivatsa. The Srivatsa method, however, requires that the physical design (in addition to the logical design) of the die be known to the designer so that the optimum number of repeaters, type of repeaters and location of each repeater may be calculated and incorporated within the physical design of the die just prior to actually physically manufacturing the die.
During the manufacturing process, there is a logical design stage and then a physical design stage. During the logical design stage, the synthesis tool converts a high-level design language (HDL) into a logical configuration while optimizing the logical interconnections required to effectuate the intended purpose(s). This conversion process is known as “synthesizing” the HDL. The floorplanning tool then groups the logic gates within functional blocks A, B, C, as described above in connection with FIG.
1
. In addition, the floorplanning tool optimizes the interconnection of the functional blocks A, B, C and, in fact, after synthesis, the logical representation (as opposed to the actual physical design) of the interconnects
120
,
125
,
130
between the functional blocks do exist.
During the physical design stage, however, the results of the floorplanning tool (i.e., the logical design) are implemented by a placement tool (e.g., Avanti or any other such placement tool known to one skilled in the art, etc.) in order to optimize the physical layout of the logic gates, functional blocks A, B, C and interconnects
120
,
125
,
130
on the die
100
. It is only after this point that the Srivatsa method can be implemented. That is, the Srivatsa method requires that a series of complex calculations be carried out where the calculations require knowledge of the physical parameters of the circuit layout. While the Srivatsa method is effective, it is overly complicated, requires many levels of calculations and generally provides a degree of accuracy not always required by the designer.
For many designs, a simplified, automated process for inserting a predetermined number of repeaters
200
within a given length of interconnect
120
would suffice. Ideally, the insertion process could be implemented with and carried out by a design tool familiar to sub-micron circuit designers. Thus, there exists a desire and need for a simplified method for automatically inserting repeater cells within sub-micron circuit designs.
SUMMARY OF THE INVENTION
The present invention overcomes the problems associated with the prior art and provides a simplified method for automatically inserting repeater cells within sub-micron designs. In accordance with an exemplary embodiment of the invention, a method is provided in which repeater cells are automatically inserted within a sub-micron design before the physical design of the die has been started. The method automatically inserts a predetermined number of repeater cells within the interconnect lines that couple functional blocks on a semiconductor die. In a preferred embodiment, the repeater cell insertion is carried out during the logical design stage by adding a series of commands within a commercially available synthesis tool. A placement tool optimizes the physical placement of the repeater cells within the die.
REFERENCES:
patent: 5801958 (1998-09-01), Dangelo et al.
patent: 5838580 (1998-11-01), Srivatsa
patent: 6009253 (1999-12-01), Srivatsa et al.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Levin Naum
Siek Vuthe
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