Leakage-tolerant memory arrangements

Details Leakage-tolerant memory arrangements Leakage-tolerant memory arrangements

2001-09-28

2003-09-30

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Accelerating charge or discharge

C365S203000, C365S194000

Reexamination Certificate

active

06628557

ABSTRACT:

FIELD OF INVENTION
The present invention is in the area of memory architecture. More particularly, the present invention provides a method, apparatus, machine-readable medium, and system for a leakage tolerant memory design.
BACKGROUND
Memory devices designed for scalability, speed, robustness, and compactness, such as a cache, may be evaluated by selecting a memory cell to be read, leaving the remainder of the memory cells coupled to the same bit-line deselected. Selecting a memory cell can comprise turning on an access transistor for the selected memory cell to allow the memory element of the cell to pull charge from the bit-line to a circuit ground. Deselecting a memory cell involves turning off the access transistors to prevent the non-selected memory cells from pulling charge from the bit-line. Even after the access transistors for the non-selected memory cells are turned off, the transistors still leak some charge and the sum of the entire off device leakage can be equivalent or greater than a single on device current, thus causing a false evaluation.
Although the leakage current of a memory cell is small, the leakage becomes a larger issue as memory arrays grow in size. A memory array increases leakage currents proportionately with growth since growth involves increasing the number of memory cells coupled to the same bit-line in parallel. When leakage currents approach or exceed the charge pulled by the selected memory cell, the sense circuitry of the memory device may require more time to distinguish or may be unable to distinguish a voltage drop due to pulling by a selected memory cell from a voltage drop due to leakage current.
Circuitry can be added to reduce leakage current or at least the effects of leakage, but adding circuitry involves trade-offs in the design of the memory devices. For example, dual-V
t
process allows high threshold (high-V
t
) transistors as access devices that will decrease the bit-line leakage current, but high threshold access devices are not as fast as low-V
t
devices. Whereas, maximizing the access speed by using low voltage threshold (low V
t
) access transistors, causes an increase in the bit-line leakage. Similarly, in full-swing single-ended memories, a keeper circuit is incorporated to replenish the leakage current. The strength of the keeper circuitry can be increased to handle increases in leakage current as memory arrays become wider, but increasing the keeper size adds cost and size to memory arrays, as well as evaluation time.


REFERENCES:
patent: 5434822 (1995-07-01), Deleganes et al.
patent: 5471421 (1995-11-01), Rose et al.
patent: 5583821 (1996-12-01), Rose et al.
patent: 6137319 (2000-10-01), Krishnamurthy et al.
patent: 6181608 (2001-01-01), Keshavarzi et al.
patent: 6204696 (2001-03-01), Krishnamurthy et al.
patent: 6225826 (2001-05-01), Krishnamurthy et al.
patent: 6429711 (2002-08-01), Tschanz et al.
Rajesh Kumar, Desktop Platforms Group-Circuit Technology, Intel Corp.; Interconnect and Noise Immunity Design for the Pentium 4 Processor, Intel Technology Journal Q1, 2001; pp. 12.

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