Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-01-17
2003-05-06
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06560762
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit wiring method for forming a portion of the structural content by connecting a plurality of circuit components that have been designed beforehand, and the associated semiconductor integrated circuit.
2. Description of the Related Art
As shown in, for example, Japanese Patent Laid-open No. 129574/96, the internal wiring of this type of semiconductor integrated circuit was typically realized by assigning a lower layer chiefly for the circuit component internal wiring and using an upper layer chiefly for wiring between circuit components with the chief aim of decreasing the number of wiring layers that are required in the integrated circuit. With the development toward miniaturization, however, the mutual interference arising between the wiring layer for connections inside circuit components used on the lower layer and the wiring layer for connections between circuit components used on the upper layer in the method of apportioning the above-described wiring layers of the prior art can no longer be ignored. As described in Japanese Patent Laid-open No. 256250/98, one known method of preventing malfunctioning of the integrated circuit arising from this interference involves forming a shielding structure that uses a conductive layer between the circuit component internal wiring and the wiring between circuit components or wiring between other adjacent circuit components.
In a typical semiconductor integrated circuit, however, methods of reducing the total amount of design that is required for development are widely used in which circuit components that have been designed beforehand are used as the constituent elements in the interest of shortening the development period. In such cases, the problem has been encountered that mutual interference resulting from the addition of inter-circuit component wiring for circuit components that were designed beforehand could not be predicted at the time of designing the circuit components, and this has resulted both in delays in the development phase due to the need to reconsider the content of circuit component design when configuring an integrated circuit and in problems with the completed integrated circuits.
In the case of Japanese Patent Laid-open No. 256250/98, moreover, a method was disclosed for sharing a shield structure against mutual interference with either the wiring for supplying the power supply potential or the wiring for supplying the around potential. In this method, the addition of wiring becomes necessary at the time of configuring the integrated circuit in order to additionally supply other potentials. This method therefore necessitates the reconsideration of the design of the circuit components because the new mutual interference brought about by the wiring addition affects the circuit components.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor integrated circuit and a semiconductor integrated circuit wiring method that keep to a minimum the need to reappraise the effects of mutual interference on the operation of circuit components and thus shorten the development stage or enable larger-scale integration.
The method of wiring a semiconductor integrated circuit according to the present invention is a method of wiring a semiconductor integrated circuit that is formed as a portion of a configuration content by connecting a plurality of circuit components that have been designed beforehand; and includes a step in which both a power supply potential wiring layer for supplying the power supply potential to the circuit components and a ground potential wiring layer for supplying the ground potential to the circuit components are provided between a wiring layer used for interconnections of nodes Inside circuit components and other wiring layers so as to generally cover the circuit components.
The method of wiring a semiconductor integrated circuit according to the present invention includes forming the power supply potential wiring layer and the ground potential wiring layer by dividing into a plurality of wiring.
The method of wiring a semiconductor integrated circuit of the present invention includes forming a portion of the internal wiring of circuit components or the wiring between circuit components on the same layer as the power supply potential wiring layer and the ground potential wiring layer.
The method of wiring a semiconductor integrated circuit of the present invention includes: forming the power supply potential wiring layer and the ground potential wiring layer independently for each circuit component for a plurality of circuit components; and moreover, configuring necessary connections to the power supply potential wiring layer and the ground potential wiring layer by using connections with another wiring layer that is positioned above the wiring layer.
The method of wiring a semiconductor integrated circuit of the present invention includes the steps of:
forming a large-scale circuit component using a plurality of small-scale circuit components; and
further configuring a semiconductor integrated circuit using a plurality of the large-scale circuit components;
wherein the above-described wiring method is applied in each of the steps.
The method of wiring a semiconductor integrated circuit of the present invention includes forming a power supply potential wiring layer and a ground potential wiring layer in a comb shape.
By adopting this type of wiring method, a layer of fixed potential that is constituted by the power supply potential wiring layer or the ground potential wiring layer provides shielding between a circuit component internal wiring layer and an inter-circuit component wiring layer, and mutual interference is thus greatly reduced.
In addition, since the power supply potential wiring layer and ground potential wiring layer both constitute the integrated circuit and serve as the necessary wiring, they can be arranged at the time of designing circuit components without necessitating an increase in the number of new wiring layers. Further, since these wiring layers are both at fixed potentials, the shape of the predetermined wiring layer can be modified according to expedience of connections with adjacent circuit components at the time of configuring an integrated circuit without causing a change in the effect on the circuit component internal wiring.
The semiconductor integrated circuit of the present invention includes:
a plurality of circuit components that have been designed beforehand and that are formed as a portion of the configuration content by connecting by wiring; a wiring layer that is used for connecting together nodes inside the circuit components;
a power supply potential wiring layer for supplying a power supply potential to the circuit components; and
a ground potential wiring layer for supplying the ground potential to the circuit components;
wherein both the power supply potential wiring layer and the ground potential wiring layer are provided between the wiring layer that is used for connecting together nodes inside the circuit components and other wiring layers so as to generally cover the circuit components.
The semiconductor integrated circuit of the present invention includes a form in which the power supply potential wiring layer and the ground potential wiring layer are each formed by dividing into a plurality of wiring.
The semiconductor integrated circuit of the present invention includes a form in which a portion of the wiring inside circuit component or the wiring between circuit components is formed by the same layer as the power supply potential wiring layer and the ground potential wiring layer.
The semiconductor integrated circuit of the present invention includes a form in which the power supply potential wiring layer and ground potential wiring layer are formed independently for each circuit component for a plurality of circuit components, and moreover,
Lin Sun James
NEC Corporation
Siek Vuthe
Sughrue & Mion, PLLC
LandOfFree
Semiconductor integrated circuit and wiring method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit and wiring method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit and wiring method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3055989