Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-10-19
2003-04-29
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06557152
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to distribution of a clock signal in a tree structure of buffer circuits in which clock skew can be reduced.
2. Description of the Related Art
A clock tree structure is conventionally known in which circuit sections in a lower layer are located at an equal distance from a circuit section as a reference point to reduce clock skews in distributed clock signals. However, when the wiring lines between the circuit sections are formed to have fine patterns,
1
the difference of the delays of a signal due to deviation in the resistance between the wiring lines cannot be ignored.
The technique to reduce clock skew is known in Japanese Laid Open Patent Application (JP-A-Heisei 7-98616). In this conventional example, the output terminals of the buffer circuits for every layer or every two or three layers are short-circuited, as shown in FIG.
1
.
Another technique to reduce the clock skew is known in Japanese Laid Open Patent Application (JP-A-Heisei 10-11494). In this conventional example, one of buffer circuits in the tree structure is selectively substituted by another buffer. As a result, the delay times (propagation times) in the buffer circuits in a same layer of the tree structure are equalized. For example, as shown in
FIG. 2
, buffer circuits BUF
3
and BUF
11
are substituted by other buffer circuits which have different threshold values from the buffer circuits BUF
3
and BUF
11
.
In case where the wiring lines are made fine, there is a limit in the first conventional example in which the delay time is adjusted through the substitution by another circuit with a different threshold value, if a clock signal with higher precision is required. Also, the second conventional example is not desired, because the wiring line becomes long for forming the short-circuit. When the clock skew is large, the effect of the short-circuit is not enough to reduce the clock skew. On contrary, the current flowing through the buffer circuit becomes large so that the possibility of erroneous operation due to noise increases. Also, the long wiring lines require a large chip area, so that the propagation time further increases.
In conjunction with the above description, a semiconductor integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-163328). In this reference, a clock driver circuit (
14
) is located in a macro cell arrangement region (
9
) in the center. The clock driver circuit (
14
) is composed of a plurality of predrivers (
15
) and main drivers (
19
). Input nodes and output nodes of the predrivers (
15
) are short-circuited by first and second common lines (
16
) and (
18
), and input nodes and output nodes of the main drivers (
19
) are short-circuited by second and third common lines (
18
) and (
20
). A plurality of clock driver circuits (
21
) are arranged in orthogonal to the clock driver circuit (
14
) with a predetermined interval. Each clock driver circuit (
21
) is composed of a plurality of predrivers (
22
) and main drivers (
25
). Input nodes and output nodes of the predrivers (
22
) are short-circuited by fourth and fifth common lines
23
and
24
, and input nodes and output nodes of the main drivers (
25
) are short-circuited by fifth and sixth common lines (
24
) and (
28
). The third and fourth common lines (
20
) and (
23
) are connected. The sixth common line (
28
) is connected to a clock signal supply line (
27
) to which a plurality of second macro cell (
26
) is connected.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a method of designing a signal distributing circuit in a tree structure of buffer circuits, in which a clock skew can be minimized.
Another object of the present invention is to provide a method of designing a signal distributing circuit in a tree structure of buffer circuits, in which a design time can be reduced.
Still another object of the present invention is to provide a method of designing a signal distributing circuit in a tree structure of buffer circuits, in which clock skew can be minimized while degradation of a clock signal can be prevented.
Yet still another object of the present invention is to provide a method of designing a signal distributing circuit in a tree structure of buffer circuits, in which a chip size can be reduced.
In an aspect of the present invention, a method of designing a signal distribution circuit, is attained by arranging and connecting a plurality of circuit patterns of buffer circuits and patterns of wiring lines to have a tree structure; by calculating a total delay time from an input of the buffer circuit in the highest layer of the tree structure to an output of each of the buffer circuits in the lowest layer of the tree structure; by selectively substituting each of the plurality of circuit patterns of the buffer circuits by one of substitution patterns of substitution buffer circuits such that the total delay times fall within a predetermined range; and by connecting all the outputs of the buffer circuits in the lowest layer of the tree structure.
It is desirable that the substitution buffer circuits have different delay times. In this case, the substitution may be attained by calculating an average of the total delay times; by determining whether a difference between each of the total delay times and the calculated average falls within a predetermined range; and by selectively substituting each of the buffer circuits in the lowest layer by one of the substitution buffer circuits based on the difference between the total delay time related to the buffer circuit and the calculated average, when the difference between the total delay time of the buffer circuit and the calculated average falls within the predetermined range.
Further, the substitution may be attained by substituting the buffer circuit in an upper layer of the tree structure related to the total delay time which does not fall within the predetermined range, by one of the substitution buffer circuits based on the difference between the total delay time and the calculated average. In this case, the substitution may further includes: selectively substituting each of the buffer circuits in the lowest layer by one of the substitution buffer circuits based on the difference between the total delay time related to the buffer circuit and the calculated average, and a difference between a delay time of the buffer circuit in the upper layer and a delay time of the substitution buffer circuit for the buffer circuit in the upper layer.
In order to achieve another aspect of the present invention, a design supporting system for a signal distributing circuit, includes a display unit, a memory which stores substitution patterns of substitution buffer circuits, and a processor. The processor controls the display unit to arrange and connect circuit patterns of a plurality of buffer circuits and patterns of wiring lines to have a tree structure. Also, the processor calculates a total delay time from an input of the buffer circuit in the highest layer of the tree structure to an output of each of the buffer circuits in the lowest layer of the tree structure. Further, the processor selectively substitutes each of the plurality of circuit patterns of the buffer circuits by one of substitution patterns of substitution buffer circuits such that the total delay times fall within a predetermined range, and connects all the outputs of the buffer circuits in the lowest layer of the tree structure.
It is desirable that the substitution buffer circuits have different delay times. In this case, the processor may calculate an average of the total delay times, and determines whether a difference between each of the total delay times and the calculated average falls within a predetermined range. Also, the processor may selectively substitute each of the buffer circuits in the lowest layer by one of the substitution buffer circuits based on the difference between the total delay time related to the buffer circuit and the calc
Liu Andrea
NEC Electronics Corporation
Scully Scott Murphy & Presser
Smith Matthew
LandOfFree
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