Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-09-29
2003-01-07
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06505334
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an automatic placement and routing method and an automatic placement and routing apparatus, which are used in designing a semiconductor integrated circuit for automatically correcting the routing layout pattern such that the wiring density becomes less than an upper limit value, and to a semiconductor integrated circuit produced by applying the automatic placement and routing method.
2. Description of Related Art
In a conventional design technique of a semiconductor integrated circuit, there is no automatic placement and routing method of automatically generating the entire layout pattern of the semiconductor integrated circuit with maintaining the wiring density at less than the upper limit value. Here, the term “wiring density” refers to a ratio of a wiring area captured by scanning a certain measurement area to the measurement area, the wiring area being obtained by summing up wiring width×wiring length of each of all wires in the measurement area. The measurement area to be scanned can be a 300 &mgr;m×300 &mgr;m region, for example. Accordingly, the wiring density is expressed as the total wiring area in the measurement area÷the measurement area, where the total wiring area=&Sgr;(width×length of each wire).
Since the wiring method of the conventional semiconductor integrated circuit is carried out as described above, if the wiring density exceeds the upper limit value in the design of the semiconductor integrated circuit, the wiring widths or placement must be corrected manually to narrow the wiring widths. This will require much manpower, presenting a problem of increasing design time and cost. In addition, the semiconductor integrated circuit with a wiring density beyond the upper limit value has problems in that it is likely to have higher wire resistance, to suffer from a break, and to reduce reliability.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide an automatic placement and routing method, an automatic placement and routing apparatus for a semiconductor integrated circuit capable of automatically controlling the wiring density in the routing design of the semiconductor integrated circuit by automatically checking the wiring density, and by correcting the routing layout pattern when the wiring density exceeds an upper limit value so that the wiring density becomes less than the upper limit value, thereby improving the efficiency of designing the routing layout pattern.
According to a first aspect of the present invention, there is provided an automatic placement and routing method of automatically controlling the wiring density, the automatic placement and routing method comprising the steps of: generating a routing layout pattern from gate level circuit information about a semiconductor integrated circuit by using an automatic placement and routing tool; scanning a predetermined measurement area in the routing layout pattern; checking whether a wiring density in the measurement area is less than a predetermined upper limit value or not as a result of the scanning; and correcting, if the wiring density exceeds the upper limit value, the routing layout pattern such that the wiring density becomes less than the upper limit value.
Here, the automatic placement and routing method may further comprise the step of generating a routing layout pattern with a wiring density less than the upper limit value.
The routing layout pattern may be a global routing layout pattern, and the automatic placement and routing method may further comprise the step of generating a detail routing layout pattern of the semiconductor integrated circuit from the corrected global routing layout pattern.
When it is found that the wiring density in a same layer exceeds the upper limit value as a result of the step of checking, the step of correcting the routing layout pattern may carry out the correction by extending wiring spacing to make the wiring density less than the upper limit value, the extension of the wiring spacing can be made by one of extending the wiring spacing at a predetermined value, extending the wiring spacing at a predetermined ratio, and extending the wiring spacing by a minimum value that makes the wiring density less than the upper limit value.
When it is found that the wiring density in a same layer exceeds the upper limit value as a result of the step of checking, the step of correcting the routing layout pattern may carry out the correction by inserting a wiring inhibited region of a predetermined width between wires to make the wiring density less than the upper limit value.
When it is found that the wiring density in a same layer exceeds the upper limit value as a result of the step of checking, the step of correcting the routing layout pattern may carry out the correction by forming part of the wiring on a different layer through contact holes to make the wiring density less than the upper limit value.
When it is found that the wiring density in a same layer exceeds the upper limit value as a result of the step of checking, and that the wiring density cannot be reduced by shifting a wide wire with a width greater than a predetermined value, the step of correcting the routing layout pattern may carry out the correction by dividing the wide wire into a plurality of narrower wires and by replacing the wide wire by the narrower wires to make the wiring density less than the upper limit value.
When it is found that the wiring density of wires formed on a same layer exceeds the upper limit value, and hence the wide wire is to be replaced by the plurality of narrow wires, the step of correcting the routing layout pattern may carry out the correction by making the width from one side to the other side of the plurality of narrow wires equal to or less than the width of the wide wire.
When it is found that the wiring density of wires formed on a same layer exceeds the upper limit value, and hence the wide wire is to be replaced by the plurality of narrow wires, the step of correcting the routing layout pattern may carry out the correction by making a sum total of widths of the plurality of narrow wires equal to the width of the wide wire.
According to a second aspect of the present invention, there is provided a semiconductor integrated circuit produced by applying the automatic placement and routing method of the first aspect.
According to a third aspect of the present invention, there is provided an automatic placement and routing apparatus for automatically controlling a wiring density, the automatic placement and routing apparatus comprising: means for generating a routing layout pattern by retrieving gate level circuit information about a semiconductor integrated circuit stored in a memory and by using an automatic placement and routing tool; means for scanning a predetermined measurement area in the routing layout pattern; means for checking whether a wiring density in the measurement area is less than a predetermined upper limit value or not as a result of the scanning; means for correcting, if the wiring density exceeds the upper limit value, the routing layout pattern such that the wiring density becomes less than the upper limit value by dividing a wire into a wiring set consisting of a plurality of wires; and means for generating the routing layout pattern with the wiring density less than the upper limit value.
Here, the means for correcting the routing layout pattern may divide the wire such that a width of the wiring set from one side to the other side is equal to or less than a width of the wire before division.
The means for correcting the routing layout pattern may divide the wire such that a sum total of widths of individual wires of the wiring set after the division is equal to the width of the wire before the division.
REFERENCES:
patent: 5889677 (1999-03-01), Yasuda et al.
patent: 6226560 (2001-05-01), Hama et al.
patent: 6260179 (
Burns Doane , Swecker, Mathis LLP
Lin Sun James
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