Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-07-16
2003-05-20
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S784000, C257S729000
Reexamination Certificate
active
06566747
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a technology for producing a semiconductor package by forming a plurality of wiring patterns on a double-sided copper clad substrate in a matrix fashion and mounting semiconductor chips on the predetermined positions on the substrate and cutting apart the substrate after sealing the entire body of the substrate by resin. More particularly, the present invention relates to semiconductor packages that are produced by forming via holes for interconnecting the top and bottom sides of the double-sided copper clad substrate at the ends of each semiconductor package and by cutting apart the substrate through a line which separates each via hole into half.
BACKGROUND OF THE INVENTION
In the conventional technology for producing a semiconductor package (hereafter also referred to as “package”) after sealing an overall substrate with a resin, a double-sided copper clad substrate (hereafter also referred to as “substrate”) is provided with inner terminals for wire connecting a semiconductor chip mounted on a top surface of the substrate. The double-sided copper clad substrate is further provided with via holes or through holes for electrically connecting outer terminals formed at the bottom surface of the substrate. Here, the via holes do not run through the substrate while the through holes run through the substrate.
The above noted via hole is a conductive hole electrically connecting two particular layers on a multi-layered substrate, which is also called an inner via when used in a multi-layered substrate having four layers or more. Compared to the through hole, the via hole is considered superior to the through hole for its high mechanical strength and a process for blocking the resin in a resin sealing process can be omitted.
For commonly using the via holes by packages neighboring to each other, via holes are formed on the outside edges of the packages and are cut into half when separating the resin sealed substrate into a plurality of packages, thereby reducing the required size of the substrate relative to the packages produced.
Conventionally, this via hole formation is done, as disclosed in Japanese Laid-Open Patent Publication No. 10-294400, by methods such as sealing the through holes formed on the substrate with a conductive material such as through electro-plating, or by removing one side layer of the copper clad substrate in a circular shape and forming holes by removing the substrate material (epoxy resin, glass epoxy resin, etc.) by a laser beam in such a way that the copper layer on the other side is remained on the substrate, then treating the inner walls of the holes with the conductive material.
However, the method of forming the through holes disclosed in the above mentioned Japanese Laid-Open Patent Publication No.10-294400 requires a special technology to secure mechanical strength during the process of forming the holes, leading to high cost.
Recently, in forming a multilayered substrate having layers as many as four, six, eight or more, a process called a build-up process is used in which inner vias are created when the substrate layers are stacked together.
Moreover, in the method that forms a via hole from one side of the copper clad layers, the copper clad layer on one surface is removed in a circular shape using an etching method. After this process, a laser beam is used to take away the substrate material to form an opening. The output power of the laser beam is adjusted so that the other side of the copper clad remains intact. An example of this formation process is shown in
FIGS. 5A
,
5
B, and
5
C.
This prior art shown in
FIG. 5
requires complex and delicate pre-settings. Further, the cross sectional shape of the opening does not show a perfect shape of a circular cylinder. Instead, it is a cylinder with a thinner end portion, i.e., a conical shape. For this reason, as shown in
FIG. 5A
, remnants of the scraps D or uncut material remains inside of the opening. As a consequence, as shown in
FIG. 5B
, it is not able to produce an adequate conductive contact area between the metal plating and the copper clad layer on the other side of the substrate when the inside of this via hole is treated with conductive plating. Furthermore, as shown in
FIG. 5C
, during the cut away process or under a shock produced from an outside force, this contact area is sometimes separated from the copper clad layer because of a thin interface E, resulting in conduction failure.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made to overcome the above-mentioned problems involved in a semiconductor package in which via holes are commonly produced with resin sealing formation of a double-sided copper clad substrate. It is an object of the present invention to provide a semiconductor package and a production method thereof which is capable of securely forming conductive paths using via holes between the top copper layer and the bottom copper layer.
It is a further object of the present invention to provide a semiconductor package and production method thereof in which contact sections in the conductive paths made of via holes will not separate even when the via holes are cut away into half, thereby achieving high reliability and high production yield.
To achieve the above mentioned goals, the semiconductor package and production method of the present invention is comprised of the following:
The semiconductor package of the present invention includes wiring patterns for a plurality of semiconductor packages between top and bottom surfaces of a double-sided copper clad substrate in a matrix manner, via holes (
3
) as conductive paths each of which connects the top and bottom surfaces of the substrate and has a long hole shape in top view so that the via hole is commonly used by the wiring patterns on both semiconductor packages, semiconductor chips mounted on predetermined positions on the wiring patterns and electrically connecting the chips with terminals, and resin for sealing an entire body of the substrate. Each of the via holes is cut into half along a short diameter when separating the substrate to form two or more semiconductor packages.
Furthermore, in the semiconductor package and production method of the present invention in which the semiconductor package (
2
) is produced by: forming wiring patterns for a plurality of semiconductor packages (
2
) between top and bottom surfaces of a double-sided copper clad substrate (
1
) in a matrix manner, forming via holes (
3
) as conductive paths each of which connects the top and bottom surfaces of the substrate in a long hole shape so that the via hole is shared by the wiring patterns on both semiconductor packages, attaching semiconductor chips (
20
) on predetermined positions on the wiring patterns and electrically connecting the chips with terminals, sealing an entire body of the substrate (
1
) with resin, and cutting the substrate (
1
) on a line which separates the via hole into half, wherein an opening of each via hole (
3
) has a long hole shape.
Furthermore, the above mentioned via hole (
3
) is formed by creating an opening on a copper layer (
10
) on one side of the double-sided copper clad substrate (
1
) by removing the copper layer through an etching process, removing a substrate material (
11
) under the opening to produce cylindrical shaped openings (
31
) and connecting the cylindrical openings so as to create the opening (
31
) of a long hole shape.
Moreover, during the resin sealing process, fluorine resin film (
40
d
) may be applied between a female metal mold (
40
) and sealing resin (
25
a
).
It should be noted that the numerals in the parentheses in the above description are used only for illustration purpose and thus the present invention is not limited to the specific example in the drawings.
REFERENCES:
patent: 5562971 (1996-10-01), Tsuru et al.
patent: 5640048 (1997-06-01), Selna
patent: 6184577 (2001-02-01), Takamura et al.
patent: 6365979 (2002-04-01), Miyajima
patent: 6400573 (2002-06-01), Mowatt et al.
Kamisaki Fumiaki
Ohuchi Tsutomu
ARS Electronics Co., Ltd.
Clark Sheila V.
Muramatsu & Associates
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