Semiconductor memory device having memory cell section and...

Details Semiconductor memory device having memory cell section and... Semiconductor memory device having memory cell section and...

2001-07-30

2003-07-08

Hu, Shouxiang (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S319000

Reexamination Certificate

active

06590255

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-301309, filed Sep. 29, 2000; and No. 2000-301380, filed Sep. 29, 2000, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same, particularly, to a nonvolatile semiconductor memory device having a memory cell section and a peripheral circuit section and a method of manufacturing the same.
2. Description of the Related Art
In general, a flash memory, which is a nonvolatile memory, includes a memory cell section and a peripheral circuit section arranged around the memory section. The memory cell section includes a cell transistor constituting a memory cell. The cell transistor is of a laminated gate structure including a floating gate and a control gate. On the other hand, the peripheral circuit section includes various delay circuits required for the control of the memory cell section and a high voltage stabilizing circuit for the writing/erasing of information. It follows that a cell transistor constituting the memory cell and a transistor constituting the peripheral circuit are formed within the chip.
In recent years, the manufacturing technology of the semiconductor device has achieved a drastic progress, and the element is being miniaturized rapidly. Also, in order to reduce the manufacturing cost, serious demands are being directed to the improvement in the efficiency of the manufacturing process. Under the circumstances, it is intended to improve the efficiency of the manufacturing process by manufacturing the flash memory by using a manufacturing process substantially equal to that for manufacturing the cell transistor and the transistor in the peripheral circuit. Since the peripheral circuit of the flash memory is manufactured by the manufacturing process substantially equal to that for manufacturing a memory cell array of the laminated gate structure, the transistor of the peripheral circuit also has a laminated gate structure.
FIG. 21A
is a plan view showing a transistor constituting the peripheral circuit of the conventional flash memory, and
FIG. 21B
is a cross sectional view along the line XXIB—XXIB shown in FIG.
21
A.
As shown in
FIG. 21B
, an element isolating region
16
of an STI (Shallow Trench Isolation) structure for separating an element region
10
is formed in a semiconductor substrate
11
. Then, a gate insulating film
12
is formed on the surface of the semiconductor substrate
11
. A first conductive layer
13
is deposited on the gate insulating film
12
, and a second conductive layer
18
is deposited on the first conductive layer
13
. An insulating film
20
is deposited on the second conductive layer
18
, and a third conductive layer
21
is deposited on the insulating layer
20
. Then, the first and second conductive layers
13
and
18
are selectively removed so as to form a gate electrode G of a laminated gate structure. Further, the third conductive layer
21
and the insulating film
20
are selectively removed, followed by depositing an insulating film
22
on the entire surface and subsequently removing selectively the insulating film
20
. As a result, formed is a contact hole exposing a part of the surface of the second conductive layer
18
. The contact hole thus formed is filled with a conductive layer so as to form a contact
23
connected to the second conductive layer
18
.
In the conventional a thin gate described above, a mask deviation caused by the shortening of lithography step, required is a fringe (allowance) on the element isolating region
16
of the opposite gate. As a result, each of the edge portions of the gate electrode G in the width direction of the gate electrode G is rendered larger by a distance B than the width of the element region
10
, as shown in FIG.
21
A. Since the distance between the elements is increased by at least twice the distance B noted above, i.e., B×2, it was difficult to diminish the chip area so that it was difficult to diminish the peripheral circuit section.
As described above, in the conventional flash memory, it was difficult to manufacture simultaneously the memory cell section and the peripheral circuit section by using substantially the same process while diminishing the chip area.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a semiconductor memory device, comprising a semiconductor layer including an element region and an element isolating region for separating the element region; a first conductive layer formed within the element region with a first insulating film interposed therebetween; a second conductive layer formed on the first conductive layer within the element region; a second insulating film formed on the second conductive layer, the second insulating film partly exposing a surface of the second conductive layer; a third conductive layer formed on the second insulating film; a fourth conductive layer formed on an exposed surface of the second conductive layer, the fourth conductive layer being electrically insulated from the third conductive layer; and a contact region electrically connected to the fourth conductive layer.
According to a second aspect of the present invention, there is provided a semiconductor memory device, comprising a semiconductor layer including an element region and an element isolating region for separating the element region; a first conductive layer formed within the element region with a first insulating film interposed therebetween; a second conductive layer formed on the first conductive layer within the element region, the second conductive layer formed on the first conductive layer extending into the element isolating region, and the second conductive layer including a first section formed on the first conductive layer and a second section formed within the element isolating region; a third conductive layer formed on the second conductive layer with a second insulating film interposed therebetween, the third conductive layer and the second insulating film exposing at least one part of a surface of the second section; and a contact region electrically connected to an exposed surface of the second section.
According to a third aspect of the present invention, there is provided a semiconductor memory device, comprising a semiconductor layer including an element region and an element isolating region for separating the element region; a first conductive layer formed within the element region with an insulating film interposed therebetween; a second conductive layer formed on the first conductive layer within the element region, the second conductive layer formed on the first conductive layer extending into the element isolating region, and the second conductive layer including a first section formed on the first conductive layer and a second section formed within the element isolating region; a third conductive layer formed on the second conductive layer and exposing at least one part of a surface of the second section; and a contact region electrically connected to an exposed surface of the second section.
According to a fourth aspect of the present invention, there is provided a semiconductor memory device, comprising a semiconductor layer including an element region and an element isolating region for separating the element region; a first conductive layer formed within the element region with an insulating film interposed therebetween, the first conductive layer, which is formed on the insulating layer, extending into the element isolating region and including a first section formed on the insulating film and a second section formed within the element isolating region; a second conductive layer formed on the first conductive layer and exposing at least one part of a surface of the second section; and a contact region electrically connected to an

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