Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2001-12-24
2003-05-06
Le, Don (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S083000
Reexamination Certificate
active
06559678
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to output buffer or driver circuits. More particularly, it relates to a node predisposition circuit for driving an output node to either a high or low level with high speed but yet with significantly reduced supply bounce and ground bounce.
2. Prior Art
As is generally well-known in the art, output buffer or driver circuits are commonly used in digital circuits to provide a means for rapidly charging or discharging an output load (i.e., data bus) to a low (logic “0”) or high (logic “1”) level. When the output buffer circuit is implemented in metal oxide semiconductor (MOS) process technology, the output buffer is commonly formed of a PMOS pull-up transistor device and an NMOS pull-down transistor device connected series between a first power supply with a positive potential VCC and a second power supply with a ground potential VSS. The connection point of the pull-up and pull-down devices is further joined to an output node.
Dependent upon the logic state of a data input signal, either the pull-up or pull-down transistor device is quickly turned ON and the other is turned OFF. Typically, when such rapid switching ON and OFF of the pull-up and pull-down transistor devices occur this results in sudden surges of current creating what is sometimes referred to as current spikes. When the connection point of the pull-up and pull-down devices is making a high-to-low transition, damped oscillation or ringing will appear at the output node referred to as “ground bounce”. Similarly, when the connection point is making a low-to-high transition damped oscillation or ringing will appear at the output node referred to as “supply bounce”.
Various approaches have been made in the prior art of output buffer circuit design for minimizing the undesired supply bounce and ground bounce without sacrificing the need for high-speed of operation. One previous technique known heretofore involves the method of pre-charging the output node to one-half of the power supply voltage VCC or VCC/2. To this end, analog circuits were utilized in conjunction with bias circuits. Although this prior art method performed satisfactorily in reducing, supply bounce and ground bounce, it suffered from the disadvantage of creating excessive static currents. In a second prior art technique, there was provided a two-phase clocking system (i.e., phase I and phase II) for eliminating or removing of the excessive static currents. However, this second prior art method was not without problems since it generated a momentary current spike through the pre-charging pull-up and pull-down devices. This momentary current spike becomes magnified in a typical memory integrated circuit chip which has as many as 16 output buffer circuits. As a consequence, the momentary current spike will be multiplied 16 times, thereby producing on the order of tens of milliamps where the switching speed is in the order of nanoseconds. This will result in a supply bounce or ground bounce voltage of several volts causing interfacing problems among the output buffer and other I.C. devices connected to the same data bus.
The present invention represents a significant improvement over the two above-described prior art methods and provides a node predisposition circuit for driving an output node of an output buffer circuit to either a high or low level with a high speed of operation but with significantly reduced supply bounce and ground bounce. This is achieved by a pre-charge pull-up circuit for generating a transition from a low logic level to an intermediate level at the output node and a pre-charge pull-down circuit for generating a transition from a high logic level to the intermediate level at the output node which utilizes a single phase system.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a node predisposition circuit for driving an output node of an output buffer circuit with significantly reduced supply bounce and ground bounce which is relatively simple in its construction, but yet overcomes the disadvantages of the prior art.
It is an object of the present invention to provide a node predisposition for driving an output node of an output buffer circuit which has a significant reduction in supply bounce and ground bounce.
It is another object of the present invention to provide a node predisposition circuit for driving an output node of an output buffer circuit which utilizes the technique of pre-charging the output node to one-half of the power supply potential with aa single phase system.
It is still another object of the present invention to provide a node predisposition circuit for driving an output node of an output buffer circuit which includes a delay circuit, a pre-charge pull-up circuit, and a pre-charge pull-down circuit.
In accordance with these and other objects of the invention, there is provided a node predisposition circuit for driving an output node of an output buffer with significantly reduced supply bounce and ground bounce which includes a delay circuit, a pre-charge pull-up circuit, and a pre-charge pull-down circuit. The delay circuit has its input connected to the output node of the output buffer circuit and has an output for generating a delayed signal. The pre-charge pull-up circuit is responsive to the delayed signal and a pre-charge signal for generating a transition from a low logic level to an intermediate level at the output node. The pre-charge pull-down circuit is responsive to the delayed signal and a complement pre-charge signal for generating a transition from a high logic level to the intermediate level at the output node.
The pre-charge pull-up circuit is formed of a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a NAND logic gate, and a pre-charge pull-up output transistor. The pre-charge pull-down circuit is formed of a third PMOS transistor, a second NMOS transistor, a third NMOS transistor, a NOR logic gate, and a pre-charge pull-down output transistor.
REFERENCES:
patent: 5377149 (1994-12-01), Gaultier
patent: 5420525 (1995-05-01), Maloberti et al.
patent: 5450019 (1995-09-01), McClure et al.
patent: 5698994 (1997-12-01), Tsuji
patent: 05206830 (1993-08-01), None
Cho James H
King Patrick T.
Law Offices of Patrick T. King
Le Don
Nanoamp Solutions Inc.
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