Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-06-28
2003-07-22
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S784000, C714S781000, C714S786000
Reexamination Certificate
active
06598203
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a punctured convolutional encoder and, more particularly, to a parallel punctured convolutional encoder for providing bit error correction at high frequencies.
2. Discussion of the Related Art
Various communications systems, such as satellite communications systems, cellular telephone communications systems, etc., transmit digital data over a communications channel, such as a wireless data link, where the digital data is modulated onto a carrier wave. Typically, the transmission of digital data over the communications channel is corrupted by noise in varying degrees which causes bit errors. Thus, bit error control coding is often employed to protect the digital data from errors during transmission. Certain encoding schemes transmit redundant bits or bit symbols, to provide the bit error control. Convolutional coding is a well known bit error control coding technique for providing redundancy for bit error correction. Convolutional encoding includes mapping the bits into coded patterns without the need to partition the bits into blocks, where the bits are combined with message bits from the digital data. Punctured convolutional coding (PCC) is a known method of convolutional coding where selected bits or bit symbols are not transmitted to reduce bandwith requirements.
FIG. 1
is a schematic type diagram of a well known serial punctured convolutional encoder
10
that provides convolutional coding of the type referred to above. A stream of digital data bits x(n), where n=0, 1, 2 . . . . , to be transmitted is sent to the encoder
10
to be convolutionally coded. The encoder
10
generates two polynomial expressions y
1
(n) and y
2
(n) from the input bits that represent the bit pattern transmitted on the communications channel that is deciphered by a decoder (not shown) in the receiver to recreate the bit stream. The polynomial expressions are mathematically selected based on the largest distance between codewords in the bit stream. The decoder is typically a Viterbi decoder that receives the polynomial expressions y
1
(n) and y
2
(n), and gives the best possible sequence of the input bits x(n), as is well understood in the art. The transmission of y
1
(n) and y
2
(n) provides the redundancy of bit patterns to determine the input bit stream x(n).
The encoder
10
includes a series of one-bit delay devices
12
-
22
, and two exclusive-OR (XOR) logic gates
24
and
26
. Each of the delay devices
12
-
22
delay the particular data bit x(n) one clock period. Therefore, the current bit n is provided at node
28
, the bit n−1 is provided at node
30
, the bit n−2 is provided at node
32
, the bit n−3 is provided at node
34
, the bit n−5 is provided at node
36
, and the bit n−6 is provided at node
38
for each clock cycle. The bits n, n−1, n−2, n−3, and n−6 are applied to the XOR gate
24
, and the bits n, n−2, n−3, n−5 and n−6 are applied to the XOR gate
26
. The polynomial expression y
1
(n)=x(n)+x(n−1)+x(n−2)+x(n−3)+x(n−6) is generated at the output of the gate
24
, and the polynomial expression y
2
(n)=x(n)+x(n−1)+x(n−2)+x(n−3)+x(n−5)+x(n−6) is generated at the output of the gate
26
. A switch
40
connects the output y
1
(n) from the gate
24
to the communications channel, and a switch
42
connects the output y
2
(n) from the gate
26
to the communications channel so that selectively activating the switches
40
and
42
causes the transmission of the bit patterns to be punctured in a desired manner.
For this punctured convolutional code, the rate is
314
, which means that for every three bits that are input into the encoder
10
, four bit symbols are output from the encoder
10
. The convolutional rate is the fraction of the digits in the codeword that are necessary to represent the desired information. The remaining fraction, here 1/4, represents the redundancy that can be used to detect and correct errors. Further, in this example, the constraint length k is seven, which represents the number of delay taps in the encoder
10
. Also, the polynomials used are g
1
equal to 171 in octal which is 001 111001, and g
2
equal to 133 in octal which is 001011011. The puncture pattern u
1
for the switch
40
is
110
and the puncture pattern u
2
for the switch
42
is 101, which continuously repeat. This puncture pattern establishes that polynomials y
1
(n) and y
1
(n+1) are transmitted, y
1
(n+2) is not transmitted, y
2
(n) is transmitted, y
2
(n+1) is not transmitted, y
2
(n+2) is transmitted, and so forth as the puncture pattern repeats. Thus, for every three input bits, four output bits or bit symbols are transmitted represented by the polynomial expression to give the 3/4 rate. The rate 3/4 code can be decoded by the available rate 1/2 decoders, which is the industry standard decoder.
The above described serial punctured convolutional code scheme is well known, and operates effectively in wireless transmission schemes. However, the known convolutional encoding for bit error correction is limited in frequency. Particularly, as the frequency of the bit rate increases, it becomes more important that the bit transmission is not bursty, and the bits keep coming without punctures. It is therefore an object of the present invention to convert the known serial punctured convolutional code scheme described above to a parallel implementation applicable for higher frequency communications without bursty data.
SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, a parallel punctured convolutional encoder is disclosed that provides convolutional coding of a stream of digital data bits in a parallel manner for high frequency transmission. The parallel convolutional encoder includes a plurality of one-bit delay devices and four XOR gates. Three consecutive bits are applied to the convolutional encoder in a parallel manner at each clock cycle, and four polynomial expressions are provided from the XOR gates in a parallel manner for each clock cycle, where certain values in the polynomial expressions are provided and certain values are not provided to conform with a particular puncture scheme of a desirable convolutional rate.
In an alternate embodiment, a concatenated Reed-Solomon TCM QAM encoder is provided that inputs a series of parallel data bits at a high frequency clock rate, and outputs a certain number of parallel output bits at another high frequency clock rate. The input bit lines and the output bit lines are selected based on the rate of a trellis code modulator within the encoder. In this embodiment, a plurality of rate buffers allow the input data to be written into the buffer in a continuous matter at an input clock, and read out at a higher frequency output clock that is gated so that the number of output clock edges equal the number of input clock edges over a certain period of inputs. A plurality of Reed-Solomon encoders map a block of 7-bit input symbols into another block of 7-bit symbols consisting of a certain input word filled by a certain number of 7-bit parity symbols. A commutator maps the 7-bit input symbols into 7-bit output symbols in a periodic scheme so that for any given period of 48 consecutive inputs, each of the 48 input symbols gets mapped only once for each output symbol. A trellis code modulator maps the 7-bit input symbol into two 4-bit output symbols using a rate 3/4 convolutional encoder, where the 4-bit symbols consist of two uncoded bits and two coded bits.
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patent: 5633881 (1997-05-01), Zehavi et al.
Chung Phung M.
Miller John A.
Northrop Grumman Corporation
Warn, Burgess & Hoffmann, P.C.
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