Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-03-17
2003-03-04
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06530074
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to integrated circuits (ICs) and, more particularly, to verifying that the correct set of masks have been used in the fabrication of an IC.
BACKGROUND OF THE INVENTION
A typical IC is a multi-layered device that includes, for example, source/drain and tub regions formed in a Si substrate (TRANSISTOR level) and a polysilicon layer used to form part of a gate stack on the substrate (POLY level). A multiplicity of interconnect layers (i.e., metal layers (METAL levels) are separated by insulating layers with windows or vias formed therein (WINDOW levels) to allow metal layers at different levels to be connected to one another. In the fabrication of each of these levels of an IC, one or more patterned quartz masks (referred to as a mask set) are used in conjunction with standard photolithography and etching techniques to transfer the patterns into the various layers of the IC. Each quartz mask has a metalized pattern thereon that defines the structure to be formed in the IC at the corresponding mask level.
Despite careful quality control procedures, from time to time an incorrect mask set is used in the fabrication of an IC. For example, ICs are prone to incorrect mask selection when multiple mask versions are generated from an original IC design, each version involving changes to one or more of the POLY, WINDOW and/or METAL mask levels. Consequently, multiple versions of an approved mask level (or mask set) may be present at the wafer fabrication facility, thus complicating the manufacturing process. In the models phase of fabrication especially, this approach is error prone due to vague/imprecise documentation of the mask changes required with each version change or due to incorrect interpretation/identification by fabrication engineers of the correct set of masks that correspond to each version. In contrast, design revisions requiring changes to mask levels prior to POLY (e.g., at the TRANSISTOR level) usually result in a completely new mask set, thereby eliminating the ambiguity.
Using an incorrect mask in most cases results in a functional change in the IC that in turn produces an extremely low (often zero) yield when the IC is tested while it is still in wafer form (i.e., before the individual ICs are separated from one another). Resolving zero yield at this level of testing involves failure analysis time to first identify the nature of the problem, and when it is mask-related to then provide the fabrication engineers with the correction.
A more insidious problem occurs when the use of an incorrect mask does not significantly impact yield, and the use of that mask goes undetected through the lengthy process from wafer fabrication, wafer and package testing, and device characterization, to customer qualification Ultimately the defective IC is shipped to the customer who receives a device that does not meet the design intent and may fail either during customer testing or end user application. This form of the problem is a major deficiency in the fabrication process, adversely affects device quality and reliability, and is likely to diminish customer confidence in the manufacturer.
In order to address this problem in the prior art, a version marker is added to all POLY and METAL masks that are regenerated for each new mask version. The marker provides a visual indication that a new POLY or METAL mask was used in the fabrication of an IC. However, these version markers are vertically stacked, so that when the wafer is viewed with a microscope, a logical OR function is produced that indicates only that at least one mask was changed. In order to insure that all of the correct version masks were used, a detailed visual check of the completed IC is required, combined with a comparison of the data base containing the correct mask requirements for each version versus the masks printed. The cross-checking process is often time consuming and is still open to interpretation (and hence error) as to which masks are required for each version.
Thus, a need remains in the art for a technique to readily and reliably identify that a correct mask set has been used in the manufacture of an IC.
SUMMARY OF THE INVENTION
In accordance with one aspect of our invention, a method of fabricating an IC includes forming a test circuit in/on the wafer to electrically indicate that a correct mask set was used during a revision of the IC design during the manufacturing process. The readout of the circuit enables the manufacturer to immediately identify that an incorrect mask set was used, thereby preventing any improperly fabricated devices from being shipped to the customer. The test circuit may be located either in a primary device area or in the corridors between the devices (ICs). In either case, the test circuit includes a plurality of test devices, each test device corresponding to a version of the mask set in which at least one mask level modification has been made. In one embodiment the test devices are verification arrays, each array including a multiplicity of n electrical paths electrically connected in parallel with one another and extending across n of the N (n<N) structural levels of the wafer/IC (e.g., the poly, window and metal levels). Each of the paths includes n actuatable, series-connected elements corresponding to the masks used to form the n structural levels. After the modification of any one of the masks in a particular version of a mask set, selected elements are actuated in the array to indicate a correct mask version. If an incorrect mask set has been used, the test circuit provides one output signal, whereas if the correct mask set was used, the test circuit provides a different output signal
In accordance with another aspect of our invention, a semiconductor wafer includes such a test circuit either within a primary IC area or within a corridor between ICs, and in accordance with yet another aspect of our invention an individual IC includes both a functional circuit and such a test circuit.
REFERENCES:
patent: 5459355 (1995-10-01), Kreifels
patent: 5550839 (1996-08-01), Buch et al.
patent: 6311316 (2001-10-01), Huggins et al.
patent: 6337479 (2002-01-01), Kley
patent: 6346427 (2002-02-01), Gardner et al.
Genetti Wayne Andrew
Sotak David George
Agere Systems Inc.
Do Thuan
Urbano Michael J.
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