Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-09-21
2003-03-04
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C438S599000, C703S015000
Reexamination Certificate
active
06530066
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention generally relates to a technique of computing the signal propagation delay in an LSI device and, more particularly, it relates to a technique that can effectively apply to a method of computing wiring capacitance and of computing cross talk delay that can get parasitic capacity depending on wiring at high speed and with great accuracy and that is capable of removing surplus margin at the time of delay prediction.
For example, as a technique that the present inventors have considered, when the signal propagation delay in a LSI designed is computed, it is necessary to determine the load capacity of the wiring of the LSI. Following methods are considered as methods of computing this wiring capacitance;
(a) A method of preparing a library of average capacity values per unit length, the values corresponding to width and wiring layer of the noted wiring, getting the length of the noted wiring from a netlist, and multiplying both capacity value per unit length and the length of the noted wiring to computing the noted wiring capacitance.
(b) A method of preparing a library of capacity values (Cbase) per unit length, the values corresponding to width and wiring layer of the noted wiring when the noted wiring is used alone, increments (&Dgr;Cpara) of capacity values of the noted wiring where there exists parallel wiring, and increments (&Dgr;Ccross) of capacity values of the noted wiring where there exists cross wiring, and getting the length of the noted wiring the lengths of the parallel wiring, and both width and number of the noted wiring from the netlist to compute the capacity of the noted wiring capacitance.
(c) A method of performing capacity simulation of the noted wiring per net.
As a method of computing the cross talk delay, for example, the Japanese Patent Application Laid-Open No. 9-147009 describes a technique of computing the signal propagation delay due cross talk. Briefly, it is a technique of determining the fluctuations in the signal propagation delay due to cross talk by referring to a function table expressing power of driving the gate (source impedance) and the locations and parallel lengths of the parallel wiring in order to predict the delay with great accuracy.
Thus, from a consequence of the inventors considering the above-mentioned computing methods of wiring capacitance, the following is apparent. As corresponding to the following, a problem about each method of said (a) and (b) will be explained.
(a) The fluctuations of the signal propagation delay cannot be expressed because the parasitic capacity is changed by high and low density resulting from arrangement of both adjacent wiring and upper-lower layer wiring. This prevents the computing of the delay form being performed with great accuracy.
(b) The values of Cbase, &Dgr;Cpara and &Dgr;Ccross have such a mutually depending relationship that values of &Dgr;cpara are different in high and low density of cross ratio of the cross wiring and those of &Dgr;ccross are different in depending on whether the adjacent wiring exists or not. Thereby, the values of Cbase, &Dgr;Cpara and &Dgr;ccross are very different from each other in selecting a model when the computing of the wiring capacitance is performed. Additionally, since this defines values of the selected model, the computed capacity values have a limit in accuracy.
(c) The operation of determining the capacity value by capacity simulation requires long time and a large memory capacity. Therefore, it is practically impossible to determine it within the period of real time that can be allowed for verifying the delay on the basis of the entire net. While methods for determining the capacity value at high speed by means of pseudo three-dimensional simulation are also used, such methods indispensably require a screening process of limiting critical paths before using them for the computation and hence cannot correspond to all the paths.
Therefore, an object of the present invention is to provide a method of computing at high speed and with great accuracy the parasitic capacity of an LSI device due to its wiring by particularly paying attention to the change in the parasitic capacity depending on high and low density of arrangement of both adjacent wiring and the upper-lower layer wiring, and is to provide a computer-readable recording medium storing the data necessary in the form of a library.
Additionally, the following is apparent about the method of computing the cross talk delay as mentioned above. That is, the operation of generating the fluctuations of the signal propagation delay as defined by the function table is limited only when the signal of a generated side is made operational within a predetermined period of time before and after the expected operating time of the signal of an affected side. However, the above described methods do not take this timing problem into consideration so that they inevitably involve the use of a surplus margin. Then, in order to reach a target of speed, power is raised to an unnecessary extent or the target speed is lowered and this consequently causes the performance of the LSI device to be lowered.
Thus, another object of the present invention is to provide a method of computing the delay due to cross talk by paying attention only to the cross talk noise that can give rise to fluctuations in the signal propagation delay so that the surplus margin may be eliminated when the delay is predicted. Still another object of the present invention is to provide a computer-readable recording medium storing the data in the form of a library.
The above-mentioned objects and other objects of the present invention as well as the novel features of the present invention will become apparent by reading the detailed description of the invention that follows below and also by referring to the accompanied drawings.
SUMMARY OF THE INVENTION
The characteristic aspects of the present invention can be summarized as follows.
According to the invention, there is provided a method of computing wiring capacitance of an LSI device comprising a step of determining parasitic capacity of the wiring of noted net from width and number of wires of other nets crossing the noted wiring of the net and the span of the wiring of other nets in the same layer and the upper and lower layers running in parallel with (adjacently relative to) the wiring of the noted net; said method being characterized in that the parasitic capacity of the wiring of the LSI device is determined on the basis of the wiring density of other nets existing around the wiring of noted net.
Preferably, in a method of computing wiring capacitance of an LSI device according to the invention, a table of wiring capacitance per unit length is generated as library in terms of the ratio of the wiring of upper-lower layers crossing wiring of the noted net (crossing ratio) relative to the length of the latter and that of the wiring of the same layer and the upper-lower layers running in parallel with the wiring of the noted net in order to determine the parasitic capacity of wiring within the LSI device.
Alternatively, in a method of computing wiring capacity of an LSI device according to the invention, a function of wiring capacitance per unit length is generated as library in terms of the ratio of wiring of upper-lower layers crossing wiring of noted net (crossing ratio) and that of the wiring of same layer and upper-lower layers running in parallel with the wiring of the noted net in order to determine the parasitic capacity of the wiring within the LSI device.
Then, the wiring of noted net is treated as a plurality of segments produced by dividing it on a via by via basis and the capacity of each segment is determined from the length of the segment, the span of the wiring of other nets in same layer and upper-lower layers running adjacently relative to the wiring and the value of width×number of wiring crossing the wiring.
According to the invention, there is also provided a computer-readable recording medium storing data for a method of computing
Isomura Satoru
Ito Yuko
Hitachi , Ltd.
Liu Andrea
Mattingly Stanger & Malur, P.C.
Smith Matthew
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