Semiconductor integrated circuit device with test circuit

Details Semiconductor integrated circuit device with test circuit Semiconductor integrated circuit device with test circuit

2000-02-08

2003-07-22

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Skew detection correction

C714S798000, C714S815000

Reexamination Certificate

active

06598187

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and more particularly, to an input circuit of a synchronous semiconductor memory unit which acquires an input signal synchronized with a reference input (clock signal) and a test method of the input circuit.
FIG. 1
is a schematic block diagram of a conventional semiconductor integrated circuit device
100
. The semiconductor integrated circuit device
100
comprises a latch circuit
40
, an input circuit
50
including first and second input terminals
41
and
42
and an internal circuit
60
. The data input terminal D of the latch circuit
40
is connected to the first input terminal
41
and the timing input terminal (clock terminal) T is connected to the second input terminal
42
. A clock signal is supplied to the timing input terminal T via the second input terminal
42
and a data signal is supplied to the data input terminal D via the first input terminal
41
. The latch circuit
40
latches the data signal in accordance with the clock signal and supplies a latched data signal from the output terminal Q to the internal circuit
60
.
As the speed and frequency of semiconductor integrated circuit devices increases, the setup and hold time of the latch circuit
40
must be reduced. Also, a test for guaranteeing the setup time and hold time of the latch circuit
40
needs to be performed. In a warranty test, two test signals are supplied from two independent signal sources (drivers) of a test device to the first and second input terminals
41
and
42
, respectively. That is, the two test signals are supplied to the data input terminal D and the timing input terminal T via the first and second input terminals
41
and
42
, respectively, so that a time difference &Dgr;ts which corresponds to the setup time as shown in FIG.
2
(
a
) and a time difference &Dgr;th which corresponds to the hold time as shown in FIG.
2
(
b
) can be generated. The setup time and hold time are guaranteed depending on whether the latch circuit
40
can normally latch data.
In an actual test performed on a semiconductor device prior to shipment, the time differences &Dgr;ts and &Dgr;th of the two test signals are set more strictly in order to account for timing skew and test margin of the test device. However, even if the setup time and hold time of the latch circuit
40
are reduced, the reduction in the timing skew of the test device is still approaching its limit. Accordingly, it is difficult to set the time differences &Dgr;ts and &Dgr;th and consider the timing skew.
A case where the warranty test for a 0.5 ns setup time is executed is described below. In this case, as shown in FIG.
3
(
a
), the test is performed so that the second test signal supplied to the data input terminal D varies 0.5 ns before the leading edge of the first test signal supplied to the timing input terminal T. However, even if the time difference &Dgr;t of the two test signals is set to 0.5 ns, as shown in FIG.
3
(
b
), each test signal is shifted over time as shown by the dotted lines according to the timing skew Tsk (for example, ±0.2 ns) of each test signal.
FIG.
3
(
c
) shows the shift of the second test signal input to the data input terminal D based on the first test signal supplied to the timing input terminal T. In this case, the relative skew Tskr of the second test signal is ±0.4 ns (±0.2 ns×2). That is, if the first test signal at time t
1
according to the maximum +0.4 ns varies, the setup time is 0.9 ns. Accordingly, even if the latch circuit
40
latches data at 0.9 ns, the 0.5 ns setup time will not be guaranteed.
That is, the timing of the two test signals needs to be set considering the maximum time difference between the first and second test signals. In other words, to guarantee the 0.5 ns setup time, as shown in FIG.
3
(
d
), the time difference &Dgr;t needs to be set to 0.1 ns. However, if the relative skew is small, the second test signal may vary after the first test signal has varied. In this case, the latch circuit
40
cannot latch data. If a test is performed in this manner by increasing the margin of the setup time Ts, a problem arises in which many test errors are generated, causing a reduced yield.
One approach to solving this problem is to reduce the timing skew Tsk of the test signal. However, to considerably reduce the timing skew, expensive test equipment is required, which increases the test cost.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor integrated circuit device which correctly conducts the warranty test of the setup time and hold time.
One aspect of the present invention provides a semiconductor integrated circuit device including a latch circuit having a data input terminal and a timing input terminal. A first input terminal is connected to the data input terminal of the latch circuit. A second input terminal is connected to the timing input terminal of the latch circuit. A delay circuit is connected between the first input terminal and the second input terminal to receive a test signal supplied to a selected one of the first and second input terminals and supply a delayed test signal to the data input terminal or the timing input terminal corresponding to the nonselected one of the first and second input terminals.
Another aspect of the present invention provides a semiconductor integrated circuit device including a latch circuit having a data input terminal and a timing input terminal. A first input terminal is connected to the data input terminal of the latch circuit. A second input terminal is connected to the timing input terminal of the latch circuit. A delay circuit is connected between the first input terminal and the second input terminal. A test signal input terminal is connected to at least one of a first node between the first input terminal and the delay circuit and a second node between the second input terminal and the delay circuit. The delay circuit receives a test signal supplied to the test signal input terminal and provides a delayed test signal to one of the first and second input terminals.
Yet another aspect of the present invention provides a semiconductor integrated circuit device including a latch circuit having a first data input terminal, a first timing input terminal and a first output terminal. A first input terminal is connected to the first data input terminal of the latch circuit. A second input terminal is connected to the first timing input terminal of the latch circuit. A delay circuit is connected between the first input terminal and the second input terminal to receive a test signal supplied to a selected one of the first and second input terminals and supply a delayed test signal to the first data and first timing input terminals corresponding to the nonselected one of the first and second input terminals. A reference latch circuit has a second data input terminal, a second timing input terminal and a second output terminal. The second timing input terminal of the reference latch circuit is connected to the first timing input terminal of the latch circuit and the second input terminal. A reference delay circuit is connected between the first data input terminal of the latch circuit and the second data input terminal of the reference latch circuit. A comparator is connected to the first output terminal of the latch circuit and the second output terminal of the reference latch circuit.
Another aspect of the present invention provides a method of testing one of a setup time and a hold time of a latch circuit of a semiconductor integrated circuit. The latch circuit has a data input terminal and a timing input terminal. First, a test signal is supplied to a selected one of the data input terminal and the timing input terminal of the latch circuit. Then, the test signal is delayed with a delay circuit. The test signal delayed by the delay circuit is provided to the other, nonselected one of the data input terminal and the timing input terminal of the latch cir

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