Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-09-02
2003-09-30
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06628136
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor packages, and more particularly to a method and apparatus for enabling wirebond testing of a semiconductor package.
In integrated circuit (“IC”) manufacturing and packaging, a semiconductor die is formed on a substrate and interconnected to the substrate by wires or leads to form a complete circuit. Recently, yields of semiconductor devices have increased and large arrays of electronic circuits have been produced on a single semiconductor substrate. These circuit arrays typically require a large number of external connections.
In one known packaging method, the integrated circuit chip package includes a metal substrate, such as a lead frame, that electrically connects the semiconductor die to external pins of the package. In this method, the lead frame and external pins are etched or stamped directly from metal. However, as integrated circuits have become smaller and more complex, the number of external pins from the package has increased. Thus, conventional metal lead frames are no longer practical for packages which demand a relatively high pin count.
One such technique for assembling integrated circuit packages to achieve high pin counts is wirebonding. In wirebonding, a plurality of bond wires are attached one at a time from a bond pad on the semiconductor die to a corresponding bond pad on the substrate. The substrate is then connected to a printed circuit board.
Wirebonding may be used in ball grid array (“BGA”) packaging. Typically, the ball grid array package includes a surface with ball pads for receiving solder balls. The solder balls are reflowed to provide electrical communication between the semiconductor die and the attached printed circuit board. The solder balls are designed to be mounted onto a plurality of corresponding terminal connections located on the surface of the printed circuit board.
During the wirebond process, the wirebonds are tested by a wirebonding test system. For example in a BGA, the wirebond forms an electrical path between the bond pad on the semiconductor die and the ball pad on the substrate. Typically, all of the electrical paths are shorted together. During this time, a current is applied to the electrical path to insure that the shorted paths are electrically grounded.
In some cases, the wirebond connections are not shorted together. In such a case, only the first wirebond is tested to insure sufficient grounding. One disadvantage to this technique is that subsequent wirebond connections are not tested. As a result, a faulty connection may be missed and cause the circuit to malfunction. Further, the ball pads may be recessed from a surface of the BGA package. These ball pads are isolated from an electrical ground. For example, a non-conductive masking layer applied to the surface of the package may block the electrical path between the bond pad and ground. The masking layer may only be etched to expose the ball pads. Yet, a separation layer equal to the thickness of the masking layer is still present between the package and the electrical ground. During the testing process, the isolated wirebonds may not be sufficiently tested or overlooked. This may result in faulty wirebond connections, and a reduced yield of the resulting semiconductor devices.
Therefore, a need exists for a method and apparatus that is capable of sufficiently connecting a pluarlity of wirebonds to an electrical ground during a wirebond testing process.
SUMMARY OF THE INVENTION
In general, the present invention is directed to an apparatus for testing a semiconductor package that includes a layer of compliant material positioned between a grounded testing surface and a plurality of ball pads. The compliant layer forms a plurality of electrical paths to ground the ball pads in the presence of an applied electrical signal.
Accordingly, in one aspect, the apparatus includes a testing surface connected to a ground. A substrate is positioned relative to the testing surface, and includes a plurality of ball pads and at least one semiconductor die disposed thereon. A layer of compliant material is positioned between the testing surface and the ball pads to form at least one electrical path between the semiconductor die and a ground through one of the plurality of ball pads. The electrical path is grounded in the presence of an applied electrical signal.
Implementations of the invention include one or more of the following. The plurality of ball pads may be formed from copper plated with nickel and gold or palladium. The compliant layer may be attached to the testing surface by an adhesive material, recessed cutout, or press fit. A portion of the substrate may be connected to circuit test equipment to supply the applied electrical signal. The semiconductor package may be a ball grid array package. The semiconductor die may be electrically connected to the substrate by wirebonding. The compliant layer may include a plurality of projections for contacting selected ones of the plurality of ball pads to form a plurality of electrical contacts therebetween. The substrate may include a plurality of holes for receiving at least one of the plurality of projections to secure or align the substrate to the compliant layer. The ball pads and the semiconductor die may be located on the same side of the substrate. The plurality of ball pads may be recessed from a surface of the substrate. Alternatively, the ball pads and the semiconductor die may be positioned on opposite sides of the substrate.
In another aspect, the invention is directed to a method for testing a semiconductor package that incudes providing a testing surface connected to a ground. A layer of compliant material is formed on a portion of the testing surface, and a substrate is positioned onto a surface of the compliant layer to form an electrical path between at least one semiconductor die on the substrate and ground through one of a plurality of bond pads formed on a surface of the substrate.
Implementations of the invention include one or more of the following. An electrical signal may be applied to the at least one electrical path to determine if the electrical path is connected to ground. A plurality of projections may be formed on a surface of the compliant layer to contact selected ones of the plurality of ball pads. A terminal having a ground may be formed on a surface of the substrate.
Other advantages and features of the present invention will become apparent from the following description, including the drawings and claims.
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Kinsman Larry D.
Roberts Stuart L.
Cuneo Kamand
Dickstein , Shapiro, Morin & Oshinsky, LLP
Kobert Russell M.
Micro)n Technology, Inc.
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