Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-05
2003-04-15
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S382000, C257S649000, C257S760000
Reexamination Certificate
active
06548871
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a MOS structure and a method of manufacturing the semiconductor device, and more particularly to an improvement for connecting portions provided at a comparatively short distance which are to be connected by a wiring while reducing a wiring capacity.
2. Description of the Background Art
First of all, terms used in this specification will be described. In the specification, “a MOS (Metal Oxide Semiconductor) FET” or “a MOS structure” widely includes those having a gate electrode constituted by a conductor other than metals following a custom of this field. In the specification, moreover, a set of “a source region” and “a drain region” will be referred to as “a source/drain region”.
There has been known the fact that a lamination structure having a polysilicon film and a metal film is effectively used as a gate electrode in place of a conventional lamination structure having a polysilicon film and a metal silicide film in order to reduce a resistance of a gate electrode of a semiconductor element (for example, a MOSFET) having a MOS structure to implement a high-speed operation when a semiconductor integrated circuit is to be manufactured. However, in the case where a metal film is used for the gate electrode, the conditions of a heat treatment are restricted for reasons of a heat resistance after the gate electrode is formed. Accordingly, it is usually necessary to drop a heat treating temperature in the heat treatment of a source/drain region to be formed after the gate electrode is formed.
As a result, there has been a problem in that the source/drain region is insufficiently activated to raise a source/drain resistance, resulting in a reduction in the driving capability of the MOSFET. Furthermore, also in the case where a tantalum oxide film is used for a gate insulating film, for example, the restrictions on the heat resistance are not removed but the same problem related to the source/drain resistance arises. In order to solve the problem, there has been proposed a method for forming a dummy gate electrode to form a source/drain before a gate electrode is formed.
As an example,
FIGS. 19
to
26
show a semiconductor device and a method of manufacturing the semiconductor device which have been disclosed in the Document “Ext. Abst. of International Electron Devices Meeting (1998) pp. 785 to 788”. A semiconductor device
151
having a sectional structure shown in
FIGS. 19 and 20
comprises a MOSFET having a metal gate electrode constituted by a replace method using a dummy gate electrode.
FIG. 19
illustrates a sectional structure taken along a cutting line A—A or a cutting line B—B in FIG.
20
.
In the semiconductor device
151
, a plurality of element regions are set in a main surface of a semiconductor substrate
51
made of single crystal silicon and a MOSFET is built in each of the element regions. An element isolating film
52
is selectively formed as a trench type element isolating region in an area between the element regions in the main surface of the semiconductor substrate
51
. The semiconductor substrate
51
and the element isolating film
52
are covered with an insulating layer
57
acting as a mold.
Openings
71
and
72
penetrating from an upper surface to a lower surface are selectively provided on the insulating layer
57
. A gate insulating film
53
is formed on a portion in the main surface of the semiconductor substrate
51
which is surrounded by the opening
71
, and a gate electrode
61
is provided on the gate insulating film
53
to fill in the opening
71
. A gate electrode
65
is buried in the opening
72
formed on the element isolating film
52
. The gate electrodes
61
and
65
are formed of the same metal.
For each of the element regions, the semiconductor substrate
51
is provided with a channel region
55
selectively exposed to the main surface and a pair of source/drain regions
70
(or
70
a
) selectively exposed to the main surface with the channel region
55
interposed therebetween. The channel region
55
is opposed to the gate electrode
61
(or
65
) through the gate insulating film
53
. Moreover, the gate insulating film
53
and the element isolating film
52
are connected integrally with each other. The gate electrodes
61
and
65
are provided across both of the gate insulating film
53
and the element isolating film
52
.
The insulating layer
57
and the gate electrodes
61
and
65
are covered with an upper insulating layer which is not shown. The source/drain regions
70
and
70
a
and the gate electrodes
61
and
65
are connected to an upper wiring layer (not shown) through a contact hole
75
which is selectively provided in the upper insulating layer.
FIGS. 21
to
26
are views showing the steps of a method of manufacturing the semiconductor device
151
. In order to manufacture the semiconductor device
151
, first of all, the step of
FIG. 21
is executed. At the step of
FIG. 21
, a semiconductor substrate
51
made of single crystal silicon which has a main surface is first prepared. Next, a trench type element isolating film
52
is selectively formed in the main surface of the semiconductor substrate
51
. The element isolating film
52
is an insulating film for isolating elements. Then, boron ions are implanted into the main surface of the semiconductor substrate
51
. Consequently, a well is formed and doping for threshold voltage regulation is carried out at the same time.
At the step of
FIG. 22
, subsequently, a thermal oxidation treatment is first carried out. Consequently, an insulating film
82
which is a silicon oxide film is formed on the main surface of the semiconductor substrate
51
. Then, a polysilicon film and a silicon nitride film are deposited on the insulating film
82
and the element isolating film
52
by using a CVD (Chemical Vapor Deposition) method. Next, the polysilicon film and the silicon nitride film are subjected to patterning by using photolithography and anisotropic etching. Consequently, a conductive layer
54
and an insulator
55
are formed. As will be described below, the conductive layer
54
and the insulator
55
serve as dummy gate electrodes.
At the step of
FIG. 23
, next, arsenic ions are selectively implanted into the main surface of the semiconductor substrate
51
by using the conductive layer
54
and the insulator
55
as shields. Consequently, a pair of source/drain regions
70
selectively exposed to the main surface are formed. A portion which is interposed between the pair of source/drain regions
70
and is selectively exposed to the main surface under the conductive layer
54
corresponds to a channel region
55
.
At the step of
FIG. 24
, first of all, a heat treatment is carried out so that a dopant introduced into the source/drain region
70
is activated. Subsequently, the insulating film
82
is selectively removed to cause the portion provided under the conductive layer
54
to remain as a gate insulating film
83
. Then, the CVD method is executed. Consequently, a silicon oxide film is deposited over the whole upper surface of a product obtained in this stage. Subsequently, a CMP (Chemical Mechanical Polishing) method is executed. Thus, the silicon oxide film is polished until an upper surface of the dummy gate electrode, that is, an upper surface of the insulator
55
is exposed. As a result, an insulating layer
57
having an upper surface flattened is formed as shown in FIG.
24
. The insulating layer
57
selectively defines an opening
71
. The conductive layer
54
and the insulator
55
are buried in the opening
71
. An upper surface of the insulating layer
57
is arranged on a level with that of the insulator
55
.
At the step of
FIG. 25
, subsequently, the conductive layer
54
and the insulator
55
, that is, the dummy gate electrodes are removed. At this time, the gate insulating film
83
is simultaneously removed as shown in FIG.
25
. The insulating layer
57
having the opening
71
cavitated serves
Horita Katsuyuki
Itoh Yasuyoshi
Kuroi Takashi
Shiozawa Katsuomi
Chaudhuri Olik
Pham Hoai
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